Method for manufacturing semiconductor device

Abstract

The invention provides a method for manufacturing a semiconductor device. The method comprises the steps of providing a semiconductor substrate, wherein the semiconductor substrate comprises an NMOS device region and a PMOS device region, and gate trenches are formed on the semiconductor substrate in the NMOS device region and the PMOS device region; forming a high-k dielectric layer on the bottomand side walls of each gate trench; forming a protective layer on the surface of the high-k dielectric layer in the NMOS device region; performing annealing treatment in an oxygen-containing atmosphere so as to form an interface layer between the semiconductor substrate and the high-k dielectric layer of the PMOS device region; and removing the protective layer. According to the method provided by the invention, the interface layer is formed at the bottom of the gate trench in the PMOS device region, and the high-k dielectric layer can protect the interface layer from being exposed in the air, so that the quality of the interface layer is significantly improved. It is difficult to form an interface layer in the NMOS device region, and the interface state is very small, so that the methodimproves the reliability of the device and improves the performance and yield of the device.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a semiconductor device. Background technique [0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase its speed. Currently, as the semiconductor industry has advanced to nanotechnology process nodes in pursuit of high device density, high performance, and low cost, the fabrication of semiconductor devices is limited by various physical limits. [0003] For smaller nanotechnology process nodes, such as 7nm and below nanotechnology process nodes, PMOS devices can use Ge channels, while NMOS devices can use III-V compound semiconductors (such as InGaAs) as channels to increase carrier density. mobility. , Positive Bias Temperature Instability (Positive Bias Temperature Instability, referred ...

AI Technical Summary

Problems solved by technology

, positive bias temperature instability (Positive Bias Temperature Instability, referred to as PBTI) and other negative effects

[0004] For III-V compound semiconductors and Ge channel FinFET devices, the quality of the interfacial layer (IL) is very important for negative bias temperature instability (Negative Bias Temperature Instability, referred to as NBTI), but how to form high-quality IL is a major challenge for III-V compound semiconductors and Ge channel devices

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