Semiconductor device and forming method thereof

Abstract

Disclosed are a semiconductor device and a forming method thereof. The method includes the following steps: providing a substrate, wherein the substrate is provided with gate structures and first protective layers located on the top surfaces of the gate structures; forming initial side walls on the sidewalls of the gate structures and the sidewalls of the first protective layers; forming first side walls on the sidewalls of the initial side walls, wherein the material of the first side walls is different from that of the initial side walls; removing part of the initial side walls after the first side walls are formed so as to form second side walls on the initial side walls, and forming grooves between the first side walls and the first protective layers, wherein the second side walls arelocated at the bottoms of the grooves and the top surfaces of the second side walls are higher than or flush with that of the gate structures; and forming second protective layers in the grooves, wherein the material of the second protective layers is the same as that of the first side walls. The method can improve the electrical properties of semiconductor devices.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a forming method thereof. Background technique [0002] In a semiconductor device, such as a flash memory, there is a gate structure for controlling the channel current, and source and drain doped regions on both sides of the gate structure, and the source and drain doped regions are used to pass through the conductive plug and the The electrical connection of the interconnect layer in the back-end process. Before forming the conductive plug, it is usually necessary to form an interlayer dielectric layer covering the gate structure and the source-drain doped region, and then form a contact hole in the interlayer dielectric layer, and the contact hole is used to accommodate the conductive plug . [0003] As the size between adjacent gate structures is continuously reduced, the size of the contact hole between the gate structures is continuous...

AI Technical Summary

Problems solved by technology

[0004] However, the electrical performance of existing semiconductor devices is poor

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