Clock Phase Separation Method Triggered by Phase-locked Loop Clock Edge
A clock edge and phase-locked loop technology, applied in the direction of automatic power control, electrical components, etc., can solve the problems of high system operating frequency, low resolution, low performance, etc., to achieve lower system operating frequency, high resolution, lower The effect of operating frequency
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specific Embodiment approach 1
[0033] Specific implementation mode one: the phase-splitting clock method triggered by the phase-locked loop clock edge described in this implementation mode, the specific process is:
[0034] Step 1, input the clock signal 100MHz to the input terminal of the phase-locked loop;
[0035] Step 2. Multiply the clock signal from 100MHz to 315MHz, shift the phase of the high-level segment of the input clock eight times, and set the phase shift angles CLK[0]~CLK[7] to 0°, 22.5°, and 45° respectively , 66.5°, 90°, 112.5°, 135°, 157.5°;
[0036] Step 3, using the edges of the eight-way clock signals after the phase-locked loop frequency multiplication and phase shifting as sixteen trigger signals;
[0037] Step 4, performing clock synchronization processing on the signal under test;
[0038] Step 5, performing timing constraints on each transmission path of the clock signal and the signal under test;
[0039] Step 6. Determine whether the measured signal levels Count[0]~Count[15] at ...
specific Embodiment approach 2
[0043] Embodiment 2: In this embodiment, Embodiment 1 is further described. The edges of the eight-way clock signals in step 3 include rising edges and falling edges of the eight-way clock signals.
specific Embodiment approach 3
[0044] Specific implementation mode three: this implementation mode further explains the first implementation mode, and the method for extracting the positions where 0→1 transition and 1→0 transition occur in Count[0]~Count[15] described in step 5 is:
[0045] Calculate Count[n] and Count[n+1]:
[0046] When event_up[n]=(~Count[n])&Count[n+1] occurs, it is the position where 0→1 jumps;
[0047] When event_down[n]=(~Count[n+1])&Count[n] occurs, it is the position of 1→0 transition;
[0048] Among them, n=0,1,...,15.
[0049] The present invention proposes a precision time interval measurement method based on FPGA, which divides the time interval measurement into two parts: "coarse" measurement and "fine" measurement. It relies on the clock phase division method to perform time interpolation, so as to obtain higher time resolution.
[0050] The most basic method in the traditional time interval measurement technology is the pulse counting method. The pulse in the pulse count...
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