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Static random access memory and fabrication method thereof

A technology of static random storage and manufacturing method, which is applied in the direction of electrical components, transistors, electric solid-state devices, etc., can solve the problems of weak anti-noise ability, large area occupied by SRAM cells, and poor stability, so as to improve anti-noise ability and suppress leakage Power consumption and transistor threshold voltage drift, the effect of convenient SRAM chip

Active Publication Date: 2018-11-23
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0012] In view of the above-mentioned shortcoming of the prior art, the object of the present invention is to provide a static random access memory unit and a manufacturing method thereof, which are used to extend the feedback time of the SRAM unit for external disturbances when the key storage nodes of the SRAM unit are in the state, and improve the storage capacity. Unit stability, while solving the problems of large occupied area of ​​SRAM units, poor stability, high leakage power consumption and weak anti-noise ability in the prior art

Method used

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  • Static random access memory and fabrication method thereof
  • Static random access memory and fabrication method thereof
  • Static random access memory and fabrication method thereof

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Embodiment 1

[0089] The present invention provides a static random memory unit, based on a PD SOI device with a body contact structure, and uses eight transistors, please refer to figure 1 , shown as a schematic diagram of the circuit principle of the SRAM unit, including:

[0090] The first PMOS pull-up transistor 101, the second PMOS pull-up transistor 201, the first NMOS pull-down transistor 102, the second NMOS pull-down transistor 202, the first NMOS access transistor 301, the second NMOS access transistor 302, the third NMOS memory Access pipe 303 and fourth NMOS access pipe 304 .

[0091] Specifically, the gate of the first PMOS pull-up transistor 101 is connected to the drain of the second PMOS pull-up transistor 201, and the drain of the first PMOS pull-up transistor 101 is connected to the second PMOS pull-up transistor 201. The gate of the transistor 201 is connected, and the source of the first PMOS pull-up transistor 101 and the source of the second PMOS pull-up transistor 20...

Embodiment 2

[0111] The present invention also provides a manufacturing method of a static random storage unit, comprising the following steps:

[0112] First, step 1) is performed to provide an SOI substrate including a back substrate, an insulating buried layer, and a top layer of silicon in sequence from bottom to top, and a shallow trench isolation structure is formed in the top layer of silicon to define an active region.

[0113] Specifically, such as Figure 8 As shown, four active regions 20a, 20b, 20c and 20d are defined, wherein these four active regions 20a, 20b, 20c and 20d are arranged in parallel in turn, and shallow trenches are formed around each active region, and the shallow trenches The track is filled with insulating material to form a shallow trench isolation structure. In this embodiment, the insulating material is silicon dioxide.

[0114]Then perform step 2) fabricate an N well 30, a first P well 40 and a second P well 50 in the top silicon according to the positi...

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Abstract

The invention provides a static random access memory and a fabrication method thereof. A pull-up transistor and a pull-down transistor both employ L-shaped gates, a floating body effect in a partially-depleted (PD) SOI device, leakage power consumption caused by a parasitic triode effect and transistor threshold voltage drift can be effectively prevented under the condition that relatively small unit area can be sacrificed (the final effective unit area can be smaller than 8 square micrometers), and the noise-resistant capability of the unit is improved; and moreover, no extra mask is introduced to the fabrication method of the static random access memory, the fabrication method is completely compatible with a traditional logic process, a central symmetric structure is employed in the unit, the matching of the size and the threshold value of a MOS tube is facilitated, array formation is also facilitated, and a static random access memory (SRAM) chip is convenient to completely customize.

Description

technical field [0001] The invention relates to the field of memory design and manufacture, in particular to a static random memory unit and a manufacturing method thereof. Background technique [0002] With the development of semiconductor technology, the size of transistors has entered deep submicron, and the scale of memory modules has been continuously expanded in response to performance requirements. The working environment of aerospace electronic equipment is harsh, and the memory unit is exposed to the radiation of various high-energy particles, while the storage unit is more sensitive to high-energy particle radiation. Traditional memory cells are generally difficult to meet radiation resistance requirements, so designers often make improvements on the basis of traditional memory cells to improve the radiation resistance of the cells. [0003] Single event effects and total dose effects are the most common and important two types of radiation effects. [0004] The ...

Claims

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Application Information

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IPC IPC(8): H01L27/11
CPCH10B10/12
Inventor 陈静王硕王本艳柴展
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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