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Method for completely removing metal layer between wafer-level soi material and glass electrostatic bonding surface

A complete removal and electrostatic bonding technology, applied in circuits, electrical components, semiconductor devices, etc., can solve the problem that the metal layer cannot be completely removed, and achieve the effect of reducing the leakage defect rate and improving the bonding quality and bonding strength.

Active Publication Date: 2020-09-15
NO 49 INST CHINESE ELECTRONICS SCI & TECH GRP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to overcome the problem that the metal layer between the wafer-level SOI material and the glass electrostatic bonding surface cannot be completely removed, and to provide a method for completely removing the metal layer between the wafer-level SOI material and the glass electrostatic bonding surface. Methods

Method used

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  • Method for completely removing metal layer between wafer-level soi material and glass electrostatic bonding surface
  • Method for completely removing metal layer between wafer-level soi material and glass electrostatic bonding surface
  • Method for completely removing metal layer between wafer-level soi material and glass electrostatic bonding surface

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specific Embodiment approach 1

[0022] The method for completely removing the metal layer between the wafer-level SOI material and the glass electrostatic bonding surface of the present invention comprises the following steps:

[0023] Step 1: Coat the top layer of silicon 1 on the SOI silicon wafer with photoresist, perform photoetching on the photoresist according to the design requirements, and then etch the top layer of silicon 1, so that a part of the top layer of silicon 1 is etched to form a sensitive resistor 2 , and finally remove the photoresist.

[0024] Step 2: performing thermal oxidation and chemical vapor deposition on the upper surface of the top layer silicon 1 and the sensitive resistor 2 in sequence to form a composite dielectric film 3 .

[0025] The top layer silicon 1 includes the sensitive resistor 2 formed by etching and the remaining part of the top layer silicon 1 etched in step 1, and the composite dielectric film 3 formed on the sensitive resistor 2 can also be called a resistance...

specific Embodiment approach 2

[0038] The difference between the second embodiment and the first embodiment is that in the second step, thermal oxidation and chemical vapor deposition are performed on the upper surface of the top silicon 1 and the sensitive resistor 2 to form a composite dielectric film 3, specifically: first, the top silicon 1 and the upper surface of the sensitive resistor 2 are thermally oxidized to form silicon dioxide SiO 2layer, and then use low pressure chemical vapor deposition method LPCVD on SiO 2 Silicon Nitride Si 3 N 4 layer, SiO 2 layer with Si 3 N 4 layer constitutes a composite dielectric membrane.

[0039] The oxidation process can be carried out in a dry, wet or dry manner.

specific Embodiment approach 3

[0041] The difference between the third embodiment and the first embodiment is that in step 2, thermal oxidation and chemical vapor deposition are performed on the upper surface of the top layer silicon 1 and the sensitive resistor 2 to form a composite dielectric film 3, specifically: first, the top layer silicon 1 and the The upper surface of the sensitive resistor 2 is thermally oxidized to form SiO 2 layer, and then use plasma enhanced chemical vapor deposition method PECVD on SiO 2 SiO 2 / Si 3 N 4 Composite layer, SiO 2 layer with SiO 2 / Si 3 N 4 The composite layer constitutes a composite dielectric membrane. SiO 2 / Si 3 N 4 Composite layer is SiO 2 Layer plus Si 3 N 4 Composite layer composed of layers.

[0042] The oxidation process can be carried out in a dry, wet or dry manner.

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Abstract

A method for completely removing a metal layer between a wafer-level SOI material and a glass electrostatic bonding surface, and relates to a microchip manufacturing method, wherein a composite dielectric film underneath themetal layer is utilized to take away residual metal and thereby completely removing metal impurities, and ensuring that the silicon layer on the bonding surface does not retainmetal impurities, and simultaneously, the quality of the silicon layer on the bonding surface is not destroyed. In the fabrication of a multilayer metal electrode containing chemically stable metal,the ideal multilayer high-temperature-resistant metal electrode is fabricated while the quality of an electrostatic bonding surface is guaranteed, and the pressure sensitive resistance is protected, and the bonding quality and bonding strength of the wafer-level SOI material in front side electrostatic bonding are improved. Compared with the average bonding strength of the front side bonding chipmanufactured by the traditional process, the average bonding strength of the front side bonding chip manufactured by the method can be improved by more than 3 times, and the leakage rate of a lead-free sealing product is obviously reduced.

Description

technical field [0001] The invention relates to a microchip manufacturing method, in particular to a method for completely removing a chemically stable metal layer between wafer-level SOI materials and glass electrostatic bonding surfaces. Background technique [0002] In the manufacture of the existing high-temperature leadless SOI pressure sensor, a front-side patterned alignment electrostatic bonding process is required. When the sensor is used for high-temperature measurement, ordinary aluminum electrodes cannot meet the requirements of high-temperature use because they are prone to electromigration, and multi-layer metal electrodes are commonly used for applications in high-temperature environments. Such multilayer electrodes usually contain chemically stable metals, such as platinum, etc. If such chemically stable metals are removed by wet etching, the corrosion time will be very long, resulting in serious lateral corrosion, and the process is unacceptable. [0003] T...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28
CPCH01L21/28
Inventor 田雷齐虹李玉玲李鑫王明伟张林超吴佐飞
Owner NO 49 INST CHINESE ELECTRONICS SCI & TECH GRP
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