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Method for producing flat free contacting surface for semiconductor nanostructures

A technology of nanostructures and nanostructures, which is applied in the field of flattened nanostructures, and can solve problems such as inability to realize applications

Active Publication Date: 2018-12-21
FORSCHUNGSZENTRUM JULICH GMBH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This electrically short-circuits the nanowire along its growth axis and therefore does not enable the application in the sense of the present invention

Method used

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  • Method for producing flat free contacting surface for semiconductor nanostructures
  • Method for producing flat free contacting surface for semiconductor nanostructures
  • Method for producing flat free contacting surface for semiconductor nanostructures

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Embodiment Construction

[0078] An unfavorable result that often occurs in conventionally evaporated nanowires with thin metal layers is identified in Fig. 1(a) with interruptions in the electrical contacts due to shadowing effects. In particular, ferromagnetic contacts, for example composed of cobalt, have a significant disturbance of the homogeneity of the magnetization, which is mandatory for several components of spintronics and is shown in Fig. 1(b) .

[0079] In Fig. 1(b), the calculated local magnetization is shown in cross-section along the cobalt contact surrounding this circular Nanowire cross-sections are laid. Here, the stated external magnetic field is applied along the main axis of the cobalt strip, ie perpendicular to the nanowire and parallel to the substrate.

[0080] Arrows inside cobalt contacts: local orientation of magnetic moments;

[0081] Highlighted in grey: localized magnetization points mostly to the right

[0082] Bright area: localized magnetization points mostly to th...

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Abstract

The invention relates to a method for producing a flat free contacting surface for semiconductor nanostructures, wherein at least one nanostructure (2) is arranged on the surface of an initial substrate (1). A first layer (3) in which at least one nanostructure (2) is embedded is applied onto the same surface of the transfer substrate (1), and a second substrate (5) is applied onto the first layer(3). The transfer substrate (1) is then separated from the first layer (3) such that the at least one nanostructure (2) embedded in the first layer has a flat free surface. According to the invention, prior to applying the at least one nanostructure (2) onto the transfer substrate (1), an additional layer (6) which can be removed by means of a solvent is applied onto the surface of the transfer substrate (1), and the transfer substrate (1) is removed from the first layer (3) using a solvent. In this manner, a planarization / layering of nanostructures and a subsequent simplified electric contacting process is allowed. When the method steps are applied in iterations, multilayers can be constructed advantageously from horizontally aligned nanowire networks for example (figure 5B).

Description

technical field [0001] The present invention relates to novel methods for planarizing nanostructures, in particular nanowires, eg prior to electrical contacting. The invention also relates to a method for vertically stacking a plurality of nanostructures, that is to say, for fabricating one or more layers with embedded nanowires or networks of nanowires or other nanostructures that can be electrically contacted. Background technique [0002] Self-organizing nanostructures, especially semiconductor nanowires, which have been the subject of intensive research for many years, could soon be used as basic building blocks in computer chips. This aspect is attributed to the significantly superior electron mobility in III / V semiconductor nanowires relative to conventional silicon CMOS technology. There are also possibilities for optoelectronic functions and the use of new types of electrically controllable magnetic functions in the field of spintronics and the use of nanowires in t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/66H01L29/06H01L29/40H01L29/775B82Y10/00B82Y40/00
CPCB82Y10/00B82Y40/00H01L29/401H01L29/66469H01L29/775H01L29/0673H01L29/20
Inventor S.黑特J.格哈茨T.舍珀斯D.格吕茨马歇尔
Owner FORSCHUNGSZENTRUM JULICH GMBH
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