A kind of lateral trench mosfet device and its preparation method

A technology of lateral grooves and devices, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., and can solve problems such as low working speed, poor reverse recovery characteristics, and high power loss

Active Publication Date: 2020-07-31
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The present invention provides a lateral MOSFET device for the problems of poor long-term application reliability caused by excessively high gate dielectric layer electric field, poor reverse recovery characteristics resulting in high power loss, and low operating speed in existing power semiconductor devices in actual circuit applications.

Method used

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  • A kind of lateral trench mosfet device and its preparation method
  • A kind of lateral trench mosfet device and its preparation method
  • A kind of lateral trench mosfet device and its preparation method

Examples

Experimental program
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Effect test

Embodiment 1

[0098] A lateral silicon carbide MOSFET provided in this embodiment has a device cell structure such as figure 2 As shown, it includes a silicon carbide P-type substrate 14 and a substrate electrode 15 arranged on the back of the silicon carbide P+ substrate 14; The N-type doped region 11 and the SiC N-type drift region 12, the doping concentration of the SiC N-type doped region 11 is higher than that of the SiC N-type drift region 12; The top layer is provided with a silicon carbide N+ drain region 13, and the upper surface of the silicon carbide N+ drain region 13 is provided with a drain metal 3; a polysilicon region is provided on the top layer on the side of the silicon carbide N-type doped region 11 away from the drain metal 3 4. The upper and lower surfaces of the polysilicon region 4 are flush with the silicon carbide N-type doped region 11, and the polysilicon region 4 and the silicon carbide N-type doped region 11 form a heterojunction with rectifying characteristic...

Embodiment 2

[0100] A lateral silicon carbide MOSFET provided in this embodiment has a device cell structure such as Figure 4 As shown, the difference from Embodiment 1 is that the substrate is an SOI substrate. The SOI substrate includes BULK region 18, SOI dielectric layer 17 and silicon carbide N+ substrate 16 from bottom to top, such as Figure 4 shown. This improvement not only isolates the substrate current, but also provides a low-resistance path for electrons, such as Figure 5 shown. Therefore, the improvement is beneficial to improve the on-state performance of the device;

Embodiment 3

[0102] A lateral silicon carbide MOSFET provided in this embodiment has a device cell structure such as Image 6 As shown, the difference from Embodiment 1 is that the polysilicon region 4 is now a Schottky contact metal 19, such as Image 6 shown. The polysilicon 4 or the Schottky contact metal 19 forms a rectifying contact with the silicon carbide N- epitaxy 9. As described in the principle of the invention, this contact has an obvious effect on optimizing the third quadrant of the device.

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Abstract

The invention relates to a lateral trench type MOSFET device, which belongs to the technical field of semiconductor power devices. The present invention forms a polysilicon region or a Schottky contact metal region on a side of a gate structure, and makes the polysilicon region or the Schottky contact metal region and the drift region form a heterojunction or a Schottky contact with rectification characteristics. Since the heterojunction or Schottky contact is a multi-sub device and the conduction voltage drop is lower than that of the traditional parasitic diode, the reverse recovery characteristics of the device can be optimized and excellent third-quadrant on-state performance can be achieved; compared with in vitro The anti-parallel diode method significantly reduces the size of the electronic power system, reduces the packaging cost, reduces the parasitic effect caused by interconnecting wires and interconnecting wires, and thus improves the reliability of the system. At the same time, an optimized design is made to solve the problem of excessively high electric field of the gate dielectric of the device, so that the long-term application reliability of the device can be improved. In addition, the preparation method of the device of the present invention is simple, controllable and easy to implement, which promotes the popularization of semiconductor power devices in many practical applications.

Description

technical field [0001] The invention belongs to the technical field of power semiconductors, in particular to a lateral trench metal oxide semiconductor field effect transistor (Lateral Trench Metal Oxide Semiconductor Field Effect Transistor, Lateral Trench MOSFET) device and a preparation method thereof. Background technique [0002] The history of mankind is a history of facing the challenges of nature. With the continuous expansion of the depth and breadth of the human industrial revolution, people are facing various crises while enjoying the convenience brought by the achievements of industrialization. As the "blood" of the industry, the sustainable utilization of energy resources has always been valued by countries all over the world. The increasing consumption of energy resources also makes people feel the "energy crisis". While seeking new energy as an alternative to fossil energy, people are also thinking about how to maximize the utilization of energy. Electric ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/06H01L21/336H01L29/78
CPCH01L29/0684H01L29/66477H01L29/78
Inventor 张金平邹华罗君轶赵阳刘竞秀李泽宏张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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