Semiconductor device and manufacturing method thereof
A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical solid-state devices, etc., can solve problems affecting device performance, substrate high voltage, etc., and achieve the effect of suppressing coupling effects
Active Publication Date: 2019-03-01
YANGTZE MEMORY TECH CO LTD
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Problems solved by technology
During the operation of the 3D NAND storage device, it is necessary to apply a high voltage to the gate device of the 3D NAND storage device through the TSV. Transient high voltage causes coupling effect between TSV and substrate, affecting device performance
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[0040] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0041] In the following description, many specific details are explained in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described here, and those skilled in the art can do so without departing from the connotation of the present invention. Similar promotion, therefore, the present invention is not limited by the specific embodiments disclosed below.
[0042] Secondly, the present invention will be described in detail in conjunction with schematic diagrams. In detailing the embodiments of the present invention, for ease of description, the cross-sectional view showing the device structure will not be partially enlarged according to th...
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The invention provides a semiconductor device and a manufacturing method thereof. A run-through through silicon via is formed in a semiconductor substrate where a 3D memory device is formed; on the periphery of the through silicon via, a reverse doping region is formed in the substrate, wherein the substrate in the reverse doping region has an opposite doping type, so that a PN junction is formedbetween the substrate and the reverse doping region; the PN junction is formed between the through silicon via and a gating tube device of the memory device, and isolation is formed therebetween, andthe coupling effect caused by the fact that high voltage is applied to the through silicon via to carry out operation of the memory device is effectively inhibited, and the influence on the performance of the gating tube device is avoided; and meanwhile, the method does not need to add an extra isolation region, the size of the chip is not increased, the layout is flexible, and the cost of the process is low.
Description
Technical field [0001] The present invention relates to the field of semiconductor devices and their manufacturing, in particular to a semiconductor device and a manufacturing method thereof. Background technique [0002] With the continuous development of semiconductor technology and the increasing requirements for integration, the planar structure of memory devices has approached the limit of actual expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a three-dimensional memory device is proposed. [0003] In an application of a three-dimensional storage device, a 3D NAND storage device can be a MOS (Metal Oxide Semiconductor) device of a peripheral circuit formed on a different substrate, and then pass the silicon pass on the 3DNAND device substrate. The electrical connection of the TSV (Though Silicon Visa) and the peripheral circuit, thereby realizing the operation of the 3D NAND storage device. During the operation of the 3D NAND ...
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Login to View More IPC IPC(8): H01L27/11556H01L27/11597H01L21/761
CPCH01L21/761H10B41/27H10B51/20
Inventor 甘程刘威陈亮吴昕陈顺福
Owner YANGTZE MEMORY TECH CO LTD