3D stacked image sensor

An image sensor and pixel array technology, applied in image communication, electric solid-state devices, semiconductor devices, etc., can solve the problems of not greatly improving the frame rate, limited chip area, slow data transmission speed, etc., to improve the frame rate, The effect of simple manufacturing process

Active Publication Date: 2019-04-05
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the current double-layer 3D stacked chip still adopts the method of reading out row by row or multi-row in groups. Due to the slow data transmission speed, after the previous frame of image exposure, it must wait for the data to b

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[0021] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be further described below in conjunction with the accompanying drawings of the specification. Of course, the present invention is not limited to this specific embodiment, and general replacements well known to those skilled in the art are also covered by the protection scope of the present invention.

[0022] The following is attached Figure 2-7 The present invention is further described in detail with specific examples. It should be noted that the drawings all adopt a very simplified form and use non-precise proportions, and are only used to facilitate and clearly achieve the purpose of assisting the description of this embodiment.

[0023] Refer to figure 2 , image 3 with Figure 4 , figure 2 Shown is a schematic structural diagram of a 3D stacked image sensor according to an embodiment of the present invention, image 3 Shown is a schemat...

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Abstract

The invention discloses a 3D stacked image sensor. The 3D stacked image sensor comprises a pixel array, an analog-to-digital conversion unit array and a memory array. The image sensor is composed of an upper layer chip and a lower layer chip stacked up and down. The pixel array includes a plurality of pixel units for converting an optical signal into an analog electrical signal and is located on the upper layer chip. The analog-to-digital conversion unit array includes a plurality of analog-to-digital conversion units for converting the analog electrical signals into digital electrical signalsand is located on the lower layer chip. The memory array includes a memory cell array and a logic circuit array, the memory cell array includes a plurality of memory cells for storing the converteddigital electrical signals, the logic circuit array includes a plurality of logic circuits for controlling reading and writing of the memory cells; and the memory array is located at the lower layer chip. The image sensor frame rate can be improved.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a 3D stacked CMOS image sensor. Background technique [0002] With the development of CMOS integrated circuit technology, the application of electronic products in daily life is becoming more and more extensive. Provided essential technical support. In practical applications, high frame rate image sensors can provide more accurate and real-time image information, and can play an important role in areas such as intelligent driving, rapid identification, and precise capture. However, in existing products, since the image data is read out and transmitted row by row, the frame rate of the image sensor is determined by the conversion and readout time of each row of data and the number of rows. For the current high-definition large pixel array, due to the constraints of the row time and the total number of rows The frame rate is greatly limited. [0003] High integration and...

Claims

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Application Information

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IPC IPC(8): H04N5/374H04N5/378H01L27/146H04N13/204
CPCH01L27/14634H04N25/76H04N25/75
Inventor 赵宇航温建新皮常明曾夕沈灵
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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