In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be further described below in conjunction with the accompanying drawings of the specification. Of course, the present invention is not limited to this specific embodiment, and general replacements well known to those skilled in the art are also covered by the protection scope of the present invention.
 The following is attached Figure 2-7 The present invention is further described in detail with specific examples. It should be noted that the drawings all adopt a very simplified form and use non-precise proportions, and are only used to facilitate and clearly achieve the purpose of assisting the description of this embodiment.
 Refer to figure 2 , image 3 with Figure 4 , figure 2 Shown is a schematic structural diagram of a 3D stacked image sensor according to an embodiment of the present invention, image 3 Shown is a schematic diagram of the connection between the upper chip and the lower chip of a 3D stacked image sensor according to an embodiment of the present invention, Figure 4 Shown is a schematic diagram of the connection between the upper chip and the lower chip of a 3D stacked image sensor according to another embodiment of the present invention. The 3D stacked image sensor is composed of two chips 11 and 12 stacked one above the other, and includes a pixel array 21, an analog-to-digital conversion unit array 22, and a memory array 23. The pixel array 21 is located on the upper chip 11, and the pixel array includes a plurality of pixel units 211 for converting optical signals into analog electrical signals. The analog-to-digital conversion unit array 22 is located on the lower chip 12, and the analog-to-digital conversion unit array 22 includes a plurality of analog-to-digital conversion units 221 for converting analog electrical signals into digital electrical signals. Of course, other circuits can also be provided on the lower chip, which will be further described later. The image sensor of the present invention also includes a memory array 23 also located in the lower chip 12. The memory array 23 includes a memory cell array and a logic circuit array. The memory cell array includes a plurality of memory cells 231 for storing digital electrical signals, and the logic circuit array includes a plurality of logic circuits for controlling the reading and writing of the memory cells. 232. The memory cell in this embodiment is a resistive memory cell RRAM. The resistive memory cell itself is composed of a special material layer. Each memory cell can realize the change of resistance under the control of a specific voltage and current sequence. The logic circuit generates different resistance values corresponding to different voltage signals to achieve 0 and 1 storage. In this embodiment, the resistive memory cell may be single-valued or multi-valued. In other embodiments, the storage unit may also be other types of new types of memory such as magnetic memory MRAM, ferroelectric memory FeRAM, phase change memory PRAM, and so on.
 In the present invention, the memory cell array is located on the lower chip 12. The logic circuit array can be located on the upper chip or the lower chip. in image 3 In the illustrated embodiment, the logic circuit array is located on the upper chip 11; Figure 4 In the illustrated embodiment, the logic circuit array is located in the lower chip 12, that is, the entire memory array 23 is located in the lower chip.
 It can be seen from the above that on the two-layer stacked chip architecture of the prior art, the present invention forms a memory cell array on the upper part of the lower chip. On the signal transmission path, the digital electrical signal after analog-to-digital conversion can be directly stored in In the memory array. Therefore, the data of the previous frame is directly stored in the memory array, and then slowly output from the memory unit without taking a long time to serially output the signal from the analog-to-digital conversion unit, so that the exposure and signal of the next frame can be performed in time Operations such as reading have improved the frame rate. In the specific implementation process, the key storage part of the memory cell in the memory array can be made of new and special materials, and epitaxially grown between any two layers of metal of the lower chip 11, without the need to add a separate memory chip, and the wiring is more Flexible and simpler process, lower manufacturing cost. As for other parts of the underlying chip, such as analog-to-digital conversion cell arrays, logic circuit arrays, and other bias clock interface circuits, they can be manufactured using traditional FSI front-illuminated technology. The pixel array of the upper chip can be manufactured by a BSI back-illuminated process. The image sensor is manufactured through a 3D stacking process. The upper chip and the lower chip can be connected by hybrid bonding. Specifically, in image 3 , The logic circuit array of the memory array is located in the lower chip, and the pixel array is connected to the analog-to-digital conversion unit array through hybrid bonding. Logic circuit arrays, memory cells, and analog-to-digital conversion to nano-element arrays are all located in the lower chip, and are connected through existing on-chip connection methods, such as metal wires. While in Figure 4 In the embodiment shown, the logic circuit array of the memory array is located on the upper chip, the logic circuit array is connected to the memory cell array through hybrid bonding, and is also connected to the analog-to-digital conversion unit through hybrid bonding, and the pixel array is connected to the analog-digital conversion unit through hybrid bonding. Number conversion unit array connection. The hybrid bonding mentioned here is a bonding process in which metal and insulators are provided on the chip bonding interface at the same time, which can provide better bonding strength.
 Please keep reading image 3 with Figure 4 In the illustrated embodiment, although the positions of the logic circuit array are different, and the connection modes of the parts in the upper and lower layers of the chips are also different, the working principles of the image sensors are the same. Specifically, the analog-to-digital conversion unit may include a comparison circuit and a quantization circuit. The comparison circuit includes two input terminals and an output terminal. The two input terminals receive the pixel unit signal and the reference voltage signal respectively, and the comparison result of the comparison circuit The output is converted into a digital electric signal by the quantization circuit, and finally the quantization circuit outputs the converted digital electric signal. The storage unit stores the digital electrical signals converted by the analog-to-digital conversion unit. The logic circuit mainly includes sub-unit modules such as read-write timing control module, sensitive amplifier module, power management, etc., and is mainly responsible for the signal writing and reading of the storage unit.
 In a preferred embodiment of the present invention, each pixel unit corresponds to an analog-to-digital conversion unit and a memory, where the memory includes at least one storage unit and at least one logic circuit. Thus, a pixel unit, an analog-to-digital conversion unit, and a memory can be regarded as a sub-unit, and as Figure 5 As shown, the image sensor can be seen as an array of these sub-units. Each pixel unit 211 is connected to an analog-to-digital conversion unit 221, and each analog-to-digital conversion unit 221 is connected to a memory. Further, the lower chip also includes a first driving circuit, a second driving circuit, and a third driving circuit. The first driving circuit is used to drive the logic circuits of the memory array to be turned on at the same time so that each digital electrical signal converted by the analog-to-digital conversion unit array is output to the memory cell array in parallel; the second driving circuit is used to drive each pixel unit to simultaneously The received optical signal is converted into an analog electrical signal; the third driving circuit is used to drive each analog-to-digital conversion unit to simultaneously convert each analog electrical signal into a digital electrical signal. In this way, all the sub-units can work at the same time, thereby significantly improving the working efficiency of the image sensor.
 It should be noted that the driving signals of each pixel unit in the present invention may be independent, or partly or completely connected together. The independent connection of the driving signal can make the use of the image sensor more flexible. In this connection mode, each pixel unit needs a first driving circuit, that is, the number of first driving circuits is the same as the number of pixel units. However, in this way, the first driving circuit occupies a larger area of the lower chip. The driving signals of the pixel units can also be all connected together, and all the pixel units of the pixel array are exposed and read at the same time. In this connection mode, the entire pixel array only needs a first driving circuit, but the first driving circuit needs sufficient driving capability . The driving of the pixel units can also be partially connected in groups. In this connection mode, the number of first driving circuits required for the entire pixel array is equal to the number of groups to be driven. This mode is a compromise between driving capability and area, but In the case of group driving, the timing of different groups should be matched. Similarly, the drive signals of the analog-to-digital conversion unit of the lower chip can be independent, can be all connected together, or can be driven in groups. Independent driving signals require more second driving circuits, connecting driving signals together requires a second driving circuit with greater driving capability, and grouping driving signals requires matching driving timing between different groups. The number of third driving circuits of the memory array of the lower chip can also be set to one according to requirements, which is the same as the number of memories or multiple groups, which will not be repeated here.
 Please refer to Image 6 , Which shows a schematic diagram of the working state of the image sensor. Since the image sensor can be regarded as an array of multiple sub-units working at the same time, the working state of the image sensor is the same as the working state of a single sub-unit. The working state of a sub-unit can be divided into 3 stages, namely exposure, frame front and signal readout. Suppose the exposure time is T_exp, the frame front time is T_fot, and the signal readout time of a pixel unit is T_row, then one frame of signal The total time for reading is T_total=T_exp+T_fot+T_row, and the frame rate is Fps=1/T_total. If the number of rows of the pixel array is N, the time for the conventional structure to read one frame of signal is T_total=T_exp+T_fot+N*T_row, and in the present invention, all digital electrical signals that undergo analog-to-digital conversion are stored in the memory In the array, and each memory, pixel unit, and analog-to-digital conversion unit have a one-to-one correspondence, each sub-unit works synchronously, and these digital electrical signals are simultaneously output to the memory array in parallel. The comparison shows that one frame of signal is read The total time is T_total=T_exp+T_fot+T_row. Compared with the prior art, the present invention greatly shortens the total time of one frame.
 Since only two voltage states of 0 or 1 need to be stored in the present invention, no matter whether the resistive storage unit is a single-value storage unit or a multi-value storage unit, each bit of the digital electrical signal output by the analog-to-digital conversion unit is connected to a resistance changer. Type storage unit. The number of storage units in each memory can be determined by the number of bits of the analog-to-digital conversion unit. As a result, the converted digital electrical signal can be written into each resistive memory cell in a parallel manner, and the total writing time is short. It should be noted that the storage unit and the logic circuit in each memory may have a one-to-one correspondence, or may not have a one-to-one correspondence. For example, in some embodiments, the same logic circuit can control all storage units in a memory to store each bit of the digital electrical signal in parallel. Refer to Figure 7 , The resistive storage unit is single-valued, and the analog-to-digital conversion unit is 10 bits (10bit), then the pixel signal output by the analog-to-digital conversion unit is D[11:1], where D[10:1] is the analog-to-digital conversion The highest bit D of the digital electrical signal converted by the unit is the sign bit. The memory includes 11 resistive storage cells, denoted as S1 to S11. The logic circuit controls to write D[11:1] into S1~S11. When the pixel signal needs to be read out, the logic circuit is set to read timing so that the pixel data of each memory is read out.
 In summary, the 3D stacked image sensor of the present invention forms a memory array on the upper surface of the lower chip, and the digital electrical signal after analog-to-digital conversion can be directly stored in the memory array, so that it will not affect the exposure of subsequent frame images. . Furthermore, since the memory array is epitaxially grown between any two layers of metal of the lower layer chip, there is no need to separately arrange the memory chip, and the manufacturing process is simpler. Furthermore, the pixel unit, the analog-to-digital conversion unit and the memory are in a one-to-one correspondence, so that a frame of image data can be transmitted at the same time, which greatly improves the frame rate of the image sensor.
 Although the present invention has been disclosed as above in preferred embodiments, the many embodiments described are only examples for convenience of description and are not intended to limit the present invention. Those skilled in the art can do without departing from the spirit and scope of the present invention. With some changes and modifications, the scope of protection claimed by the present invention should be subject to the claims.