High-speed digital logic circuit for SAR_ADC and sampling regulation method

Abstract

The invention belongs to the technical field of analog or digital-analog hybrid integrated circuits, and relates to a high-speed SAR_ADC digital logic circuit, in particular to a high-speed digital logic circuit for SAR_ADC and a sampling regulation method. The digital logic circuit comprises a comparator and a logic control unit which are parallel, and a capacitor array DAC, wherein the comparator and the logic control unit are simultaneously triggered by a clock signal; the comparator outputs an effective comparison result Dp / Dn, the logic control unit outputs a corresponding rising edge signal, a delay matching is set to make the rising edge signal output the Dp / Dn a little later than the comparator, and the Dp / Dn is captured by the corresponding rising edge signal to create a capacitorarray. The circuit eliminates the disadvantage of error establishment of a capacitor array brought by that the traditional parallel digital logic uses a digital logic window to capture the output result of the comparator, which can maximize the adoption time of SAR_ADC in the case of asynchronous logic.

Description

technical field [0001] The invention belongs to the technical field of analog or digital-analog hybrid integrated circuits, and relates to a high-speed SAR_ADC digital logic circuit; specifically, a high-speed digital logic circuit and a sampling adjustment method for the SAR_ADC. Background technique [0002] In recent years, with the further improvement of the performance index of the analog-to-digital converter, especially with the continuous development of the integrated circuit process technology, the research on the high-speed asynchronous successive approximation analog-to-digital converter has become more and more in-depth. With the continuous evolution of integrated circuit manufacturing processes, the design of high-gain operational amplifiers has become more and more difficult. Since no operational amplifiers are required, SAR structure ADCs have a natural advantage of low power consumption, especially at nanoscale process nodes. SAR The speed of the structure ADC...

AI Technical Summary

Problems solved by technology

In order to obtain higher sampling accuracy, in the design, methods such as increasing the size of the sampling switch, reducing the area of ​​the DAC, or reducing the conversion speed of the SAR_ADC must be used. The above methods will significantly increase the design cost or introduce other non-ideal factors, increasing the circuit design. difficulty

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