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Fabrication method of nanowire device

A manufacturing method and nanowire technology, which is applied in semiconductor/solid-state device manufacturing, nanotechnology, nanotechnology, etc., can solve the problems of relatively high manufacturing process requirements for the inner wall, and achieve the effects of low process requirements, avoiding damage, and improving performance

Active Publication Date: 2022-02-22
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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Problems solved by technology

[0006] The main purpose of this application is to provide a method for manufacturing a nanowire device to solve the problem of relatively high manufacturing process requirements for the inner wall of the nano-devices in the prior art

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  • Fabrication method of nanowire device
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  • Fabrication method of nanowire device

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[0023] It should be pointed out that the following detailed description is exemplary and intended to provide further explanation to the present application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0024] It should be noted that the terminology used here is only for describing specific implementations, and is not intended to limit the exemplary implementations according to the present application. As used herein, unless the context clearly dictates otherwise, the singular is intended to include the plural, and it should also be understood that when the terms "comprising" and / or "comprising" are used in this specification, they mean There are features, steps, operations, means, components and / or combinations thereof.

[0025] It will be understood that when an element such as a layer, film, region, or substrate is referred to as ...

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Abstract

The present application provides a method for fabricating a nanowire device. The fabrication method includes: step S1, forming a laminated part and a dummy gate on the surface of the substrate, the laminated part is located on the surface of the substrate and includes alternately arranged GeSi layer and the Ge layer, the dummy gate is located on the surface of the stack part away from the substrate; step S2, using an oxidation process, so that silicon oxide is generated at both ends of the GeSi layer, germanium oxide is generated at both ends of the Ge layer, and the Ge The germanium oxide generated in the layer is oxidized, so that a filling gap of predetermined length is formed between the remaining Ge layer and the adjacent GeSi layer with silicon oxide at both ends; step S3, setting the inner wall material in the filling gap, Form the inner wall. This manufacturing method can easily form the inner wall of predetermined length.

Description

technical field [0001] The present application relates to the field of semiconductors, in particular, to a method for fabricating a nanowire device. Background technique [0002] As nanodevices enter the technology node of 7nm and below, nanowires have become the most promising device structure. Among them, the inner wall process is one of the key processes to realize the integration of nanowires. If there is no inner wall process, the length of the gate formed when the nanowire is released is relatively wide, which affects device performance; even if the S / D selective etching and epitaxy process is used, the length of the dummy gate and the dummy gate will be released when the nanowire is released. The sum of the lengths of the sidewalls on both sides of the gate will still increase the subsequent length of the gate. [0003] Therefore, only the process of source-drain etching + inner wall process + source-drain selective epitaxy can form a controllable minimum gate lengt...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/06H01L21/336B82Y10/00
CPCH01L29/66545
Inventor 李永亮马雪丽李俊杰王晓磊杨红王文武李超雷
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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