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Manufacturing method of sonos device

A manufacturing method and device technology, which is applied in semiconductor devices, electric solid devices, photoplate-making process of patterned surface, etc., can solve the problems of cost increase and high cost, and achieve the effect of reducing process cost

Active Publication Date: 2022-03-04
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since adding a photolithography process will increase the cost, the photolithography definition of the ONO layer of the storage tube in the existing method will increase the cost

Method used

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  • Manufacturing method of sonos device
  • Manufacturing method of sonos device
  • Manufacturing method of sonos device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0038] Such as figure 1 As shown, it is a flow chart of the manufacturing method of the SONOS device of the embodiment of the present invention, such as Figure 2A to 2J As shown, it is a device configuration diagram in the various steps of the embodiment of the present invention. The SONOS device in the manufacturing method of the SONOS device of the present invention includes a storage area 101 and a high pressure region 102 located other than the storage area 101. The operating voltage of the high voltage region 102 is greater than the operating voltage of the memory area 101, the memory area 101 including the unit structure of the SONOS device, the unit structure including the storage tube 103 and the selection tube 104, the select tube 104 For NMOS tube, the high voltage region 102 includes a high pressure NMOS tube 105 and a high pressure PMOS tube 106. Figure 2A In the memory region 101, respectively, the autoclave 102 is located on both sides of the dashed line AA, the stor...

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PUM

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Abstract

The invention discloses a method for manufacturing a SONOS device, which comprises the steps of: forming a shallow trench on a semiconductor substrate; photoetching to open the formation area of ​​a storage region and performing deep well implantation; filling the shallow trench with an oxide layer; forming a second A sacrificial oxide layer; photolithography forms the first photoresist pattern to open the formation area of ​​the storage tube and implants the channel region forming the storage tube; removes the first sacrificial oxide layer in the storage tube formation area and then removes the photoresist; grows ONO layer; photolithography opens the formation area of ​​the P-type device, removes the ONO layer in the open area and implants it to form the channel region of the P-type device; photolithography opens the formation area of ​​the N-type device, removes the ONO layer in the open area and implants it to form N The channel region of the type device; the first sacrificial oxide layer is removed to form a gate dielectric layer outside the storage tube; and the polysilicon gate is formed. The invention can save a photoresist plate used to define the ONO layer separately, thereby reducing the process cost and not changing the performance of the device.

Description

Technical field [0001] The present invention relates to a method of manufacturing a semiconductor integrated circuit, particularly a method of manufacturing a SONOS device. Background technique [0002] As the size of the chip continues to shrink, the function is increasing, and the process cost is continuously increased. Saving a photolithography and reduction process steps without affecting device performance, it is a primary consideration for reducing process costs. For SONOS devices, a storage area is typically included and a high voltage region located outside of the storage area, the operating voltage of the high voltage region is greater than the operating voltage of the memory area, the memory area including the unit structure of the SONOS device. The unit structure includes a storage tube and a selection tube, the selection tube as an NMOS tube; the high pressure zone comprises a high pressure NMOS tube and a high pressure PMOS tube. The gate dielectric layer of the stor...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/1157H01L27/11524H01L21/28G03F7/00H10B43/35H10B41/35
Inventor 单园园郭振强陈瑜胡君
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP