High-frequency clock synchronization circuit based on clock swallowing circuit

Abstract

The invention discloses a high-frequency clock synchronization circuit based on a clock swallowing circuit. The circuit comprises a clock swallowing circuit, a frequency divider, a phase discriminatorand a digital circuit, wherein a high-frequency clock input signal is output to the frequency divider through the clock swallowing circuit; frequency division clock signals are obtained after being processed by the frequency divider; the frequency division clock signal is processed by the phase discriminator to output a first sampling signal and a second sampling signal, the first sampling signaland the second sampling signal are processed by the digital circuit to output an indication signal for controlling the clock swallowing circuit, and the synchronization of the frequency division clock signal and the clock synchronization signal is realized by combining the synchronization signal.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a high-frequency clock synchronization circuit based on a clock swallowing circuit. Background technique [0002] At present, applications including communication, radar, and data transmission need to meet the requirements of clock synchronization. As the frequency of the signal to be synchronized becomes higher and higher, the design of the synchronization circuit becomes more and more difficult. When the traditional synchronization scheme can no longer meet the requirements, a new synchronization scheme is urgently needed to solve the demand for high-frequency clock synchronization. [0003] In the prior art, clock synchronization is mainly realized by means of asynchronous reset. However, as the clock frequency becomes higher and higher, the timing constraints required for asynchronous reset become more and more stringent. Designing a clock circuit wi...

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Problems solved by technology

However, as the clock frequency becomes higher and higher, the timing constraints required for asynchronous reset become more and more stringent. Designing a clock circuit with a high-speed asynchronous reset function requires a large cost in circuit power consumption and chip area. Under specific process conditions Can't even meet design timing requirements at all

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