Multi-debugging mode circuit suitable for special processor and monitoring simulation method thereof

Abstract

The invention discloses a multi-debugging mode circuit suitable for a special processor and a monitoring simulation method thereof which are achieved based on a nested function state machine during design. The circuit comprises a main state machine circuit for command packet analysis, a program execution sub-state machine circuit and a data feedback sub-state machine circuit, wherein the circuit has a simple structure and better practical expansibility. The program execution sub-state machine circuit integrates four debugging functions of single step execution, breakpoint execution, complete execution and register value monitoring together through an address determination circuit and a state machine instruction generation circuit, and achieves multiple debugging modes after key addresses in a command packet are analyzed; the data feedback sub-state machine circuit provides two data feedback modes according to the start-stop address of the memory recorded by the address monitoring circuit, and can meet different simulation requirements.

Description

technical field [0001] The invention belongs to the field of embedded system hardware, and in particular relates to a multi-debugging mode circuit suitable for a special processor and a monitoring simulation method thereof. Background technique [0002] There is a dedicated processor that adopts an improved Harvard structure, including two independent memory modules FLASH and SRAM, and an independent address bus and data bus. FLASH and SRAM respectively store instructions and data. When the processor is working, the two buses are time-shared by the program memory and the data memory. They are jointly controlled by the processor's memory chip select signal and the read-write enable signal. The two buses are accessed by using the common address bus memory, and the common data bus is used to complete the data transfer between the program memory or data memory and the CPU. [0003] For processor simulation, the existing simulation technologies mainly include five types: commerc...

AI Technical Summary

Problems solved by technology

The 16-bit processor is characterized by the use of RISC reduced instruction set architecture, which includes primary and secondary registers, has no special simulation structure, and does not have embedded simulation circuits, so it can only be implemented using ROM monitoring simulation technology based on custom development boards. Simulation, but the existing ROM monitoring simulation technology is based on the reference prototype design of a dedicated processor chip. In order to meet the needs of different debugging modes, the circuit design is more complicated, the implementation cost is high, and the practical scalability is poor.

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