A voltage-resistant sub-threshold cmos reference source circuit

Abstract

A withstand voltage sub-threshold CMOS reference source circuit, comprising a start-up circuit, a main circuit and a booster circuit, the start-up circuit is used to ensure the normal opening of the main circuit, the main circuit is used to generate a reference voltage vbg, and the booster circuit is used to The base voltage vbg is raised to the base reference voltage vref. By adding multi-layer transistors between the power supply voltage vdd and the reference voltage vbg, the withstand voltage of the sub-threshold CMOS reference source is improved, and the precision and power supply voltage rejection ratio of the sub-threshold CMOS reference source are also improved.

Description

technical field [0001] The invention relates to a sub-threshold CMOS reference source circuit with withstand voltage. Background technique [0002] With the continuous decline of process nodes, the voltage of devices under advanced processes continues to decrease, but there are often high voltages in the external interface level. In the process of designing a chip, a reference source with a withstand voltage structure (such as a power supply voltage of 3.3V and a device withstand voltage of only 1.8V) is usually required. Secondly, due to the large scale of the chip, in order to reduce the chip area and power consumption, sometimes a reference source with a sub-threshold CMOS structure is used. The sub-threshold state MOS transistor refers to a working state in which the gate-source voltage Vgs of the MOSFET is below the threshold voltage VT but there is no conductive channel, that is, Vgs≤VT and the surface potential ψs≈Fermi potential ψb (that is, the surface is weak Inv...

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Problems solved by technology

[0004] figure 1 In the subthreshold CMOS structure, due to the difference in the substrate potential of the M1 and M2 tubes, the lining bias effect occurs, which will cause a difference in the threshold voltage of the two tubes; the difference in the source-drain voltage of the M3 and M4 tubes will affect the accuracy of the current mirror. , thus affecting the accuracy of the reference voltage; there are only two layers of tubes between the power supply and the ground, and this structure cannot withstand high voltage; the disturbance on vdd will directly act on the potential of point C and be coupled to vbg through the parasitic capacitance between the gate and drain of the M8 tube, thereby deteriorating the high frequency power supply voltage rejection ratio

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