3D NAND memory and forming method thereof

Abstract

A 3D NAND memory and a forming method thereof are disclosed. According to the forming method of the 3D NAND memory, at least one pseudo common source penetrating a stacking structure is formed in gateisolation groove regions, gate isolation grooves penetrating the stacking structure are subsequently formed in the gate isolation groove regions on the two sides of the pseudo common sources, and thegate isolation grooves formed on the two sides of the pseudo common sources expose the corresponding side walls of the pseudo common sources. In the process of forming the gate isolation grooves, inthe process of removing a sacrificial layer after the formation of the gate isolation grooves and in the process of forming control gates and array common sources, the pseudo common sources can support the two side walls of the gate isolation grooves and prevent the two side walls of the gate isolation grooves from deforming or tilting. Thus, the stability of the characteristic dimensions of the formed gate isolation grooves is ensured, and the performance of the 3D NAND memory is improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for reducing 3D NAND memory. Background technique [0002] NAND flash memory is a non-volatile storage product with low power consumption, light weight and good performance, and has been widely used in electronic products. At present, the NAND flash memory with a planar structure is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory with a 3D structure is proposed. [0003] The formation process of the existing 3D NAND memory generally includes: forming a stacked structure in which isolation layers and sacrificial layers are alternately stacked on the substrate; etching the stacked structure, forming channel vias in the stacked structure, and forming channel vias Finally, etch the substrate at the bottom of the channel via hole to form a groove in the substrate; in ...

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Problems solved by technology

[0004] Existing memories generally include several memory blocks (Blocks), and the gate spacers between the memory blocks generally pass through the stack structure in the vertical direction, and the gate spacers on both sides of the pseudo-common source are exposed. The sidewall (Gate Line Slit, GLS) corresponding to the pseudo common source is separated, but in the manufacturing process of the existing 3D NAND memory, the characteristic size of the gate spacer is easy to fluctuate, which affects the performance of the memory

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