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Automatic fault injection method of EDIF netlist-level combinational logic circuit

A technology of combinational logic circuits and fault injection, which is used in the detection of faulty computer hardware, electrical digital data processing, instruments, etc.

Active Publication Date: 2019-09-06
HARBIN ENG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to solve the existing simulation-based fault injection needs to solve the interface problem with EDA simulation software, and propose an automatic fault injection method for EDIF netlist-level combinational logic circuits

Method used

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  • Automatic fault injection method of EDIF netlist-level combinational logic circuit
  • Automatic fault injection method of EDIF netlist-level combinational logic circuit
  • Automatic fault injection method of EDIF netlist-level combinational logic circuit

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Experimental program
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specific Embodiment approach 1

[0022] Specific implementation mode one: the specific process of the automatic fault injection method of a kind of EDIF netlist level combinatorial logic circuit of this embodiment is:

[0023] The root cause of circuit failures is the physical defects in the manufacturing process, which show errors under certain incentive conditions, and eventually lead to system failure when the errors exceed a certain limit. Defect types include silicon wafer defects, photolithography defects, mask problems, process deviations and oxidation problems, such as large bubbles in materials, surface ions, irregular tilting or shape deformation of components or connecting lines, etc. Since there are many causes of physical failures and are related to the process, generally the physical failures are not studied directly, but the modeled logical failures are studied. Common logical fault models of integrated circuits include stuck-at faults, bridging faults, transient faults, and time-delay faults. ...

specific Embodiment approach 2

[0035] Specific embodiment two: the difference between this embodiment and specific embodiment one is that the original netlist file is traversed in the step one, and the original netlist file is preprocessed; the specific process is:

[0036] Extract all the network cables in the original netlist file, remove the initial input and output, and construct the network cable list $Nets, which is convenient for subsequent insertion of fault points.

[0037] Other steps and parameters are the same as those in Embodiment 1.

specific Embodiment approach 3

[0038]Specific embodiment 3: The difference between this embodiment and specific embodiment 1 or 2 is that in the step 3, forward traversal is performed according to the fault point, and the network cable corresponding to the fault point is deleted by reverse search to the input terminal of the logic gate The logic gate $toDel_Gate connected to $Net, and the logic gate associated with the network cable corresponding to the fault point (the logic gate in the fan-in area); the specific process is:

[0039] First find the logic gate $toDel_Gate whose output terminal is connected to the network cable $Net corresponding to the fault point, and then call the function Del_Gates($EDIF_str, $toDel_Gate) to delete the logic that the output terminal is only connected to the network cable $Net corresponding to the fault point Door.

[0040] Among them, the Del_Gates($EDIF_str, toDel_Gate) function is a recursive function, and its pseudocode is described as follows:

[0041]

[0042] T...

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Abstract

The invention discloses an automatic fault injection method of an EDIF netlist-level combinational logic circuit, and relates to an automatic fault injection method of a circuit. The invention aims tosolve the problem that the interface with EDA simulation software needs to be solved in the conventional simulation-based fault injection. The method comprises the following steps: 1, processing an original netlist file; 2, selecting one network cable to inject Sa-0, setting a fault point; 3, carrying out forward traversal; 4, carrying out backward propagation; 5, generating a fault equivalent circuit, and judging whether Sa-is injected or not; 1, turning to 6; 7, turning to 7; 6, judging whether a network cable without a fault exists or not, and if yes, turning to 2-6; if not, ending fault injection; 7, injecting Sa-1 into the second middle network cable;, setting fault points; carrying out forward traversal; 8, performing backward propagation to judge whether the input value affects thefunction of the logic gate or not; 10, judging whether a network cable without a fault exists or not, and turning to 7-10; judging whether fault injection is finished or not. The method is applied tothe field of automatic fault injection of circuits.

Description

technical field [0001] The invention relates to automatic fault injection methods for circuits. Background technique [0002] The primary task of automatic testing of digital circuits is to determine a set of test vectors for all faults in the circuit to be tested. By injecting faults and applying excitation to the circuit under test in the EDA environment, the response of the circuit in the fault state can be obtained. On the one hand, it can speed up the search process of effective test vectors by accelerating circuit failure, and on the other hand, it is convenient for designers to carry out circuit fault tolerance. and reliability analysis. [0003] Fault injection is to artificially generate faults according to the fault model, and implant them into the circuit under test through a certain strategy to induce errors. Common fault injection methods include physics-based fault injection and simulation-based fault injection. The former achieves fault injection at the phy...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50G06F11/26
CPCG06F11/261G06F30/33G06F30/327
Inventor 姚爱红刘咏梅林明宇田啸天李玉坤
Owner HARBIN ENG UNIV
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