An automatic fault injection method for edif netlist-level combinational logic circuits

A technology of combinational logic circuits and fault injection, which is used in the detection of faulty computer hardware, electrical digital data processing, instruments, etc.

Active Publication Date: 2022-07-08
HARBIN ENG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The purpose of the present invention is to solve the existing simulation-based fault injection needs to solve the interface problem with EDA simulation software, and propose an automatic fault injection method for EDIF netlist-level combinational logic circuits

Method used

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  • An automatic fault injection method for edif netlist-level combinational logic circuits
  • An automatic fault injection method for edif netlist-level combinational logic circuits
  • An automatic fault injection method for edif netlist-level combinational logic circuits

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specific Embodiment approach 1

[0022] Embodiment 1: The specific process of an automatic fault injection method for an EDIF netlist-level combinational logic circuit in this embodiment is:

[0023] The root cause of circuit failure is a physical defect in the manufacturing process, which exhibits errors under certain excitation conditions, and eventually leads to system failure when the error exceeds a certain limit. Defect types include wafer defects, lithography defects, mask problems, process deviations, and oxidation problems, such as large bubbles in the material, surface ions, irregular tilting or shape deformation of components or connecting lines. Because the causes of physical failures are many and related to the process, physical failures are generally not studied directly, but modeled logical failures. Common logic fault models of integrated circuits include fixed faults, bridging faults, transient faults and time-delay faults. The fixed fault model mainly reflects the uncontrollability of a sig...

specific Embodiment approach 2

[0035] Embodiment 2: The difference between this embodiment and Embodiment 1 is that in step 1, the original netlist file is traversed, and the original netlist file is preprocessed; the specific process is:

[0036] Extract all network cables in the original netlist file, remove the initial input and initial output, and construct a network cable list $Nets, which is convenient for subsequent insertion of fault points.

[0037] Other steps and parameters are the same as in the first embodiment.

specific Embodiment approach 3

[0038]Embodiment 3: The difference between this embodiment and Embodiment 1 or 2 is that in step 3, forward traversal is performed according to the fault point, and the network cable corresponding to the fault point is deleted by reverse search to the input end of the logic gate. The logic gate $toDel_Gate connected to $Net, and the logic gate associated with the network cable corresponding to the fault point (the logic gate in the fan-in area); the specific process is:

[0039] First find the logic gate $toDel_Gate whose output terminal is connected to the network cable $Net corresponding to the fault point, then call the function Del_Gates($EDIF_str, $toDel_Gate) to delete the logic that the output terminal is only connected to the network cable $Net corresponding to the fault point Door.

[0040] Among them, the Del_Gates($EDIF_str,toDel_Gate) function is a recursive function, and its pseudocode is described as follows:

[0041]

[0042] The backward propagation process...

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Abstract

An automatic fault injection method for an EDIF netlist-level combinational logic circuit relates to an automatic fault injection method for circuits. The purpose of the present invention is to solve the problem of the interface between the existing simulation-based fault injection and EDA simulation software. The process is: 1. Process the original netlist file; 2. Select a network cable to inject into Sa-0 and set the fault point; 3. Carry out forward traversal; 4. Carry out backward propagation; 5. Generate a fault equivalent circuit, Judge whether to inject Sa-1, if no, go to 6; if yes, go to 7; 6. Judge whether there is a network cable with no fault set, go to 2 to 6; if no fault injection is over; 7. Inject Sa-1 into the second network cable, set Fault point; perform forward traversal; 8. Perform backward propagation to determine whether the input value affects the function of the logic gate; The present invention is used in the field of automatic fault injection of circuits.

Description

technical field [0001] The present invention relates to an automatic fault injection method for circuits. Background technique [0002] The first task of automatic testing of digital circuits is to determine a set of test vectors for all faults in the circuit to be tested. By injecting faults and applying excitation to the circuit under test in the EDA environment, the response of the circuit in the fault state can be obtained. On the one hand, the search process of effective test vectors is accelerated by accelerating circuit failure, and on the other hand, it is convenient for designers to carry out circuit fault tolerance. and reliability analysis. [0003] Fault injection is to artificially generate faults according to the fault model, and implant them into the tested circuit through a certain strategy to induce the occurrence of errors. Commonly used fault injection methods include physical-based fault injection and simulation-based fault injection. The former realiz...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/323G06F11/26
CPCG06F11/261G06F30/33G06F30/327
Inventor 姚爱红刘咏梅林明宇田啸天李玉坤
Owner HARBIN ENG UNIV
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