Preparation method of thin film transistor and thin film transistor
A technology of thin film transistors and metal layers, applied in transistors, semiconductor/solid-state device manufacturing, semiconductor devices, etc., can solve problems such as copper/molybdenum undercut and hollowing, galvanic corrosion, etc., to reduce defective rate and improve reliability , to avoid the effect of undercut and hollowing phenomenon
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Embodiment 1
[0045] Such as figure 1 As shown, it is a flow chart of a method for manufacturing a thin film transistor provided in an embodiment of the present disclosure. The method for manufacturing a thin film transistor (thin film transistor, TFT) includes the following steps:
[0046] Step S10: providing a substrate 10, and forming a patterned first gate insulating layer 20 and a first photoresist layer 30 on the surface of the substrate 10;
[0047] In this embodiment, the substrate 10 is a glass substrate. It can be understood that in other embodiments, the substrate 10 is not limited to being a glass substrate. Specifically, the step S10 includes the following steps:
[0048] Step S101: sequentially depositing the first gate insulating layer 20 and the first photoresist layer 30 on the substrate 10; specifically, as Figure 2A As shown, the first gate insulating layer 20 is located on the substrate 10, the first photoresist layer 30 is located on the first gate insulating layer 2...
Embodiment 2
[0064] Such as image 3 As shown, the thin film transistor provided in the embodiment of this disclosure, the thin film transistor is prepared by the preparation method in the first embodiment, including:
[0065] Substrate 10;
[0066] The gate 501 includes a first metal layer 40 and a second metal layer 50, the first metal layer 40 is located on the substrate 10, and the second metal layer 50 is located on the first metal layer 40;
[0067] The gate insulating layer includes a first gate insulating layer 20 and a second gate insulating layer 70, the first gate insulating layer 20 is located on the substrate 10; the second gate insulating layer 70 is located on the On the first gate insulating layer 20 and covering the second metal layer 50;
[0068] an active layer 80 located on the second gate insulating layer 70;
[0069] a source-drain metal layer 90 located on the active layer 80; and
[0070] The source 901 and the drain 902 are disposed on the source-drain metal la...
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Abstract
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