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Power chip pre-packaging method and structure, power chip packaging method and structure and wafer pre-packaging structure

A power chip and packaging structure technology, which is applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., can solve the problems of low reliability of devices, pollution of chip terminals, etc., to improve quality, avoid pollution, and save packaging links and cost effects

Active Publication Date: 2019-09-24
GLOBAL ENERGY INTERCONNECTION RES INST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In view of this, an embodiment of the present invention provides a power chip prepackage, a packaging method and its structure, and a wafer prepackage structure, so as to solve the problems that the existing power chip packaging method will pollute the chip terminal and the reliability of the device is low.

Method used

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  • Power chip pre-packaging method and structure, power chip packaging method and structure and wafer pre-packaging structure
  • Power chip pre-packaging method and structure, power chip packaging method and structure and wafer pre-packaging structure
  • Power chip pre-packaging method and structure, power chip packaging method and structure and wafer pre-packaging structure

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Embodiment 1

[0030] An embodiment of the present invention provides a power chip prepackaging method, which is used for a wafer, and a plurality of power chips are arranged in an array on the wafer, the first electrode of the power chip is located on the first surface of the wafer, and the second electrode of the power chip Located on the second surface of the wafer, the power chip can be any one of double insulated gate transistors, fast recovery diodes and silicon carbide metal-oxide semiconductor field effect transistors. When the power chip is an IGBT, the first electrode may be a collector of the power chip. Such as figure 1 As shown, the power chip prepackaging method includes the following steps:

[0031]S101: Fix the multiple first lead-out electrodes 11 on the same plane through the first encapsulation layer 21 . Specifically, packaging material can be used to fill the spaces between the first extraction electrodes 11 to form a first packaging layer 21 surrounding the first extr...

Embodiment 2

[0039] The embodiment of the present invention also provides a power chip packaging method, the power chip packaging method includes the following steps:

[0040] The prepackaged power chip obtained according to the power chip prepackaging method described in Embodiment 1 is packaged by a crimping package process.

[0041] When the pre-packaged power chip is packaged by the press-fit packaging process, such as image 3 As shown, the pre-packaged power chip 100 can be packed into the packaging shell 200, and placed on the boss of the lower cover 400, and the upper cover 300 is applied on top, so as to complete the packaging of the press-fit power device.

[0042] In the power chip packaging method provided by the embodiment of the present invention, when the pre-packaged power chip is packaged by using the crimping packaging process, since the power chip is pre-packaged, the power chip is protected from the influence of the packaging process to the greatest extent. Therefore, ...

Embodiment 3

[0044] The embodiment of the present invention also provides a wafer pre-packaging structure, such as Figure 2D As shown, the wafer pre-packaging structure includes: a wafer 4, the wafer 4 includes a plurality of power chips 42 arranged in an array, the first electrode 43 of the power chip 42 is located on the first surface of the wafer, and the first electrode 43 of the power chip 42 Two electrodes 41 are located on the second surface of the wafer; a plurality of first lead-out electrodes 11 are respectively connected to the first electrodes 43; the first encapsulation layer 21 fills the space between each first lead-out electrodes 11, and is connected to the wafer The first surface of 4 is separated; a plurality of second extraction electrodes 12 are connected to the second electrodes 41 respectively; the second encapsulation layer 22 fills the space between each second extraction electrodes 12 .

[0045] The wafer pre-packaging structure provided by the embodiment of the p...

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Abstract

The invention discloses a power chip pre-packaging method and structure, a power chip packaging method and structure and a wafer pre-packaging structure. The power chip pre-packaging method is applied to a wafer, wherein the wafer is provided with multiple power chips arranged in an array, a first electrode of each power chip is located on the first surface of the wafer, and a second electrode of each power chip is located on the second surface of the wafer. The pre-packaging method includes the steps of fixing multiple first extraction electrodes on the same plane through a first packaging layer; arranging the wafer on the first extraction electrodes, wherein the first surface of the wafer faces towards the first extraction electrodes; respectively arranging multiple second extraction electrodes on the second electrodes of the power chips; filling the space between the second extraction electrodes by a packaging material to form a second packaging layer surrounding the second extraction electrodes; and cutting the wafer to form pre-packaged power chips. The implementation of the method avoids the possibility that the power chip terminal is polluted and improves the reliability of the power chips.

Description

technical field [0001] The invention relates to the technical field of power devices, in particular to a power chip prepackage, a package method and its structure, and a wafer prepackage structure. Background technique [0002] Power semiconductor devices usually refer to power electronic devices with a passing current of tens to thousands of amps and a withstand voltage of hundreds of volts, and are mainly used for power conversion of power equipment. Power semiconductor devices include insulated gate bipolar transistors (Insulated Gate Bipolar Transistor, IGBT), silicon carbide metal-oxide semiconductor field effect transistors (SiC MOSFET) and other devices. Among them, IGBT is a voltage-controlled power electronic device with input impedance Large, small driving power, simple control circuit, small switching loss, fast switching speed, high operating frequency, large component capacity, no absorption circuit, etc., have been widely used in industrial converters, electric...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/56H01L21/60H01L21/78H01L23/31H01L23/488
CPCH01L21/561H01L21/78H01L23/3114H01L23/3135H01L23/488H01L24/94
Inventor 武伟王亮张喆唐新灵吴军民潘艳张朋李现兵
Owner GLOBAL ENERGY INTERCONNECTION RES INST CO LTD
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