Semiconductor structure and formation method thereof

Abstract

The invention discloses a semiconductor structure and a formation method thereof. The method comprises the steps of providing a substrate, a fin portion and channel laminations located on the fin portion, wherein each channel lamination comprises sacrificial layers and channel layers, if the number of the channel laminations is two, the sacrificial layer close to the top of the channel laminationis a first sacrificial layer, the remaining sacrificial layer is a second sacrificial layer, and if the number of the channel laminations is greater than or equal to three, at least one sacrificial layer close to the top of the channel lamination is a first sacrificial layer, and the remaining sacrificial layers are second sacrificial layers; forming a pseudo gate structure; etching the channel lamination layers on two sides of the pseudo gate structure to form grooves; etching part of the first sacrificial layer exposed out of the groove to form a first trench; forming a first barrier layer in the first trench; etching part of the second sacrificial layer exposed out of the groove to form a second trench, wherein the depth of the second trench is greater than that of the first trench; forming a second barrier layer in the second trench; forming a source-drain doping layer in the groove; and forming a metal gate structure at the positions of the pseudo gate structure, the remaining first sacrificial layer and the remaining second sacrificial layer. The forming quality of the metal gate structure is improved according to the invention.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] In semiconductor manufacturing, with the development trend of VLSI, the feature size of integrated circuits continues to decrease. In order to better meet the requirements of scaling down the device size, the semiconductor process has gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as forming a gate-all-around gate with fins (Gate-all-around, GAA) transistor. In a fully surrounded gate transistor, the gate surrounds the area where the channel is located. Compared with a planar transistor, the gate of a fully surrounded gate transistor has a stronger ability to control the channel and can better suppress the short channel effect. . [0003] When the size of semiconductor devices is reduced to a certain extent, how to...

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Problems solved by technology

[0005] However, after introducing the barrier layer, the device performance still needs to be improved

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