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36results about How to "Reduce the difficulty of formation" patented technology

Forming method of metal-oxide semiconductor (MOS) transistor source drain stress area and manufacturing method of MOS transistor

The invention relates to a forming method of a metal-oxide semiconductor (MOS) transistor source drain stress area, which comprises the steps that: a semi-conductor substrate is provided, and a sacrifice grid is formed on the semi-conductor substrate; ions are implanted into the semi-conductor substrate, and an amorphous area is formed in the semi-conductor substrate on both sides of the sacrifice grid; a dielectric layer which contains inherent stress is formed on the semi-conductor substrate; the semi-conductor substrate is annealed; and a source drain stress area is formed in the amorphous area on both sides of the sacrifice grid. The forming method of the MOS transistor source drain stress area reduces the difficulty in filling a stress film above a source drain is reduced and greatly improves the stress conversion proportion to a channel by directly forming the dielectric layer which contains the inherent stress on the source drain area on both sides of a grid to introduce stress. Simultaneously, the semi-conductor substrate which is pre-amorphousized in the source drain area transfers the stress into the source drain area, so that the stress of an original etched dielectric layer and a channel area after a side wall is formed is still maintained, and the stress changes improve the carrier mobility.
Owner:INST OF MICROELECTRONICS CHINESE ACAD OF SCI

Small-pore-diameter narrow-distribution polytetrafluoroethylene microporous membrane and preparation method thereof

The invention discloses a preparation method of a small-pore-diameter narrow-distribution polytetrafluoroethylene microporous membrane. By mixing of dispersible polytetrafluoroethylene resin, solventoil and a surface active agent and adopting the processes of ageing, blank manufacture, pushing and squeezing, calendaring, oil removal, longitudinal pulling treatment, horizontal pulling treatment, sintering and sizing and the like, the polytetrafluoroethylene microporous membrane with the pore diameter being 10-50nm and the bubble-point pore diameter being less than 80nm is manufactured; the surface active agent is added into a formula, and by the action of the surface active agent, the wettability of the solvent oil is obviously improved, and the wrapping degree of the solvent oil to the polytetrafluoroethylene resin is obviously improved, so that the formation degree of micropores in the drawing and expanding processes is greatly reduced; under the action of same shearing force, the formed micropores are more and smaller, so that the microporous membrane with small pore diameter and narrow distribution is obtained; the preparation method is easy in industrial production, can utilize the existing manure equipment only in need of proper process adjustment, and has strong practicability and wide applicability.
Owner:华设设计集团环境科技有限公司

GaN-based HEMT low-temperature gold-free ohmic contact electrode and preparation method thereof

PendingCN112670336AEnhanced ohmic contactMitigate Electronic LeakageSemiconductor/solid-state device manufacturingSemiconductor devicesPhysicsEtching
The invention discloses a GaN-based HEMT low-temperature gold-free ohmic contact electrode. The GaN-based HEMT low-temperature gold-free ohmic contact electrode comprises a GaN-based HEMT epitaxial layer, wherein a GaN channel layer is arranged in the GaN-based HEMT epitaxial layer. The electrode comprises a first metal layer Ti, a second metal layer Al and a third metal layer TiW which are sequentially arranged on the upper surface of the GaN-based HEMT epitaxial layer from bottom to top, or a first metal layer Ti, a second metal layer Al, a third metal layer Ti and a fourth metal layer TiW which are sequentially arranged from bottom to top. The invention also correspondingly discloses a preparation method of the electrode. According to the invention, the annealing temperature of GaN-based HEMT ohmic contact is effectively reduced, 2DEG leakage caused by overall etching of an AlGaN barrier layer and current reduction during ohmic contact forming are improved, ohmic contact forming difficulty is reduced, and the appearance and edge of an ohmic contact surface after low-temperature alloy annealing are smoother. Meanwhile, the manufacturing cost of a GaN-based HEMT device can be reduced.
Owner:ZHONGSHAN INST OF MODERN IND TECH SOUTH CHINA UNIV OF TECH +1

Close cutting fracturing method

ActiveCN112177583AIncrease the amount of liquidRealize centralized liquid intakeFluid removalThermodynamicsSingle stage
The invention relates to a close cutting fracturing method. The method comprises the steps that shale parameters are evaluated, and fracture parameters and fracturing construction parameters are optimized; perforation operation of the first time is carried out; fracturing treatment is carried out, and a liquid rubber plug carrying a propping agent is injected after fracturing treatment is finished; displacement operation is carried out; perforation operation of the second time is carried out; fracturing treatment and displacement operation are carried out; ball throwing temporary plugging is carried out on transformed perforation clusters; fracturing treatment is carried out on perforation clusters which are not transformed; displacement operation is carried out; a bridge plug is tripped in, and the above steps are repeated until construction of all sections is completed; and plug drilling after pressing, flowback, testing and production are carried out. 5-8 clusters of high-difficultyoperation are converted into 3-stage fracturing operation through two times of perforation operation and ball throwing temporary plugging in a single section, and therefore conventional 3-6 clustersof the single section are reduced into 1-2 clusters of the single stage fracturing operation, the liquid inlet amount of a single cluster is increased, the requirement of fracturing construction for displacement is reduced, and a construction pressure window is enlarged; and meanwhile, the horizontal principal stress difference is reduced through the stress shadow effect, the fracture complexity is improved, and the transformation size of a deep shale gas well is increased.
Owner:CHINA PETROLEUM & CHEM CORP +1

A close-cut fracturing method

ActiveCN112177583BReduced displacement requirementsFacilitate control of the opening sequenceFluid removalThermodynamicsPrincipal stress
The invention relates to a close-cut fracturing method. The method includes: evaluation of shale parameters and optimization of fracture parameters and fracturing construction parameters; performing a first perforation operation; fracturing treatment; liquid rubber plug of the agent; replacement operation; carry out the second perforation operation; fracturing treatment, replacement operation; temporary plugging of the reconstructed perforation cluster; fracturing treatment for the unmodified perforation cluster; replacement operation; next Insert the bridge plug, repeat the above until all constructions are completed; drill the plug after pressing, flow back, test and produce. Through two perforation operations and temporary plugging in a single stage, the difficult operation of 5-8 clusters was transformed into a 3-stage fracturing operation, thereby reducing the conventional single-stage 3-6 clusters to a single-stage 1-2 cluster fracturing operation, increasing the single-cluster fluid intake, reducing the demand for displacement in fracturing construction, and increasing the construction pressure window; at the same time, the horizontal principal stress difference is reduced through stress shadowing, which increases the complexity of fractures and increases the depth of Shale gas well stimulation volume.
Owner:CHINA PETROLEUM & CHEM CORP +1

Semiconductor structure and forming method thereof

The invention discloses a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate; the gate structure is separated from the substrate and comprises a gate contact region which is in contact with the gate plug; the source-drain doped region comprises a source-drain contact region and a source-drain connection region; the dielectric structure layer is positioned on the substrate at the side part of the gate structure and covers the source-drain doped region and the gate structure; the source-drain contact structure is in contact with the source-drain doped region, the source-drain contact structure is of an integrated structure and comprises a source-drain plug penetrating through the dielectric structure layer of the source-drain contact region and a source-drain contact layer located in the dielectric structure of the source-drain connection region, and the top surface of the source-drain contact layer is lower than the top surface of the source-drain plug; the source-drain contact structure and the dielectric structure layer enclose an interval opening; the interval dielectric layer is filled in the interval opening; and the gate plug is positioned at the top of the gate structure of the gate contact region and is in contact with the gate structure. According to the embodiment of the invention, the source-drain contact structure is an integrated structure, and the electrical connection performance between the source-drain plug and the source-drain contact layer is improved.
Owner:SEMICON MFG INT (SHANGHAI) CORP +1

Three-dimensional memory, preparation method thereof and electronic equipment

The invention provides a three-dimensional memory, a preparation method thereof and electronic equipment. The preparation method comprises the following steps: providing a substrate; forming a first laminated structure on one side of the substrate; forming a plurality of first channel holes which penetrate through the first laminated structure and extend to the substrate; forming an etching barrier layer filling the first channel holes; forming a second laminated structure on the first laminated structure and the etching barrier layer; forming a plurality of second channel holes penetrating through the second laminated structure; and removing the etching barrier layer to enable the first channel holes and the second channel holes to be communicated to form channel holes. The channel holes,which are formed in one step in related technologies, are formed in two steps in the method of the invention. The first channel holes close to the bottom are first formed, and then the other second channel holes communicated with the first channel holes are formed. According to the forming method provided by the invention, the forming difficulty of the channel holes can be reduced, the channel holes with excellent structures are formed, and the uniformity of the depth of the channel holes is improved.
Owner:YANGTZE MEMORY TECH CO LTD

A kind of semiconductor device and its forming method

Disclosed in the invention is a semiconductor device comprising a semiconductor substrate, a semiconductor drift region, base electrode regions, source regions, a grid dielectric layer, a grid electrode, metal pre dielectric layers, and a second electrode. To be specific, a first electrode is formed at one side of the semiconductor substrate. The semiconductor drift region is formed by a first drift region, a second drift region, and a third drift region; and the first drift region, the second drift region, and the third drift region are stacked at the other side of the semiconductor substrate upwardly in sequence. The base electrode regions are formed inside the third drift region. The source regions are formed inside the base electrode region. The grid dielectric layer is formed on the third drift region and is located between the two base electrode regions. The grid electrode is formed on the grid dielectric layer. The metal pre dielectric layers are formed around the grid electrode and at the top of the third drift region except the portion between the two source regions. The second electrode is formed on the grid electrode, the metal pre dielectric layers, and the third drift region between the two source regions. In addition, the invention also discloses a forming method of the semiconductor device. Therefore, the charge balance capability of the super junction drift region can be effectively improved.
Owner:SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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