36results about How to "Reduce the difficulty of formation" patented technology

The invention discloses positive lead plaster for a lead-acid storage battery and a preparation method of the positive lead plaster. The positive lead plaster is characterized by consisting of the following raw materials by weight percent: 7 to 10 percent of 1.4g / ml dilute sulfuric acid, 8 to 12 percent of deionized water, 5 to 20 percent of red lead, 0.1 to 0.4 percent of colloid graphite, 0.1 to 0.3 percent of stannous sulfate, 0.1 to 0.3 percent of anhydrous sodium sulfate, 0.2 to 0.5 percent of 4BS, 0.1 to 0.3 percent of diantimony trioxide, 0.05 to 0.2 percent of polyester short fibers, and the balance being lead powder. After the lead plaster which is prepared by utilizing the formula and the preparation method is prepared into the storage battery, the storage battery has the characteristics of high primary capacity, long service life, good low-temperature performance and good charging capacity.

The invention discloses a cooling process for a green pole plate of a lead-acid storage battery after curing, and aims to overcome the defects that the cooling time is long after the pole plate of the storage battery is cured and a lattice structure between an active substance on a surface of the pole plate and a grid is not stable so as to improve defective rate of the pole plate, and the surface of the pole plate is easy to carbonize so as to improve the formation difficulty of the pole plate and reduce the capacity and the cycle lifetime of the battery. The cooling process comprises the following steps of (a) placing the green pole plate which is cured just now in a curing chamber under a normal-temperature environment for normal-temperature cooling for 0.5-1.5 hours; (b) performing temperature reduction on the curing chamber placed with the green pole plate, adjusting a temperature to 5-10 DEG C, simultaneously blowing air by a fan, and controlling time for 2-3 hours; and (c) placing the green pole plate in the curing chamber under a room-temperature ventilation environment for 0.5-1 hour, wherein pole separation and brush can be performed.

The invention discloses a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate; the gate structure is separated from the substrate and comprises a gate contact region which is in contact with the gate plug; the source-drain doped region comprises a source-drain contact region and a source-drain connection region; the dielectric structure layer is positioned on the substrate at the side part of the gate structure and covers the source-drain doped region and the gate structure; the source-drain contact structure is in contact with the source-drain doped region, the source-drain contact structure is of an integrated structure and comprises a source-drain plug penetrating through the dielectric structure layer of the source-drain contact region and a source-drain contact layer located in the dielectric structure of the source-drain connection region, and the top surface of the source-drain contact layer is lower than the top surface of the source-drain plug; the source-drain contact structure and the dielectric structure layer enclose an interval opening; the interval dielectric layer is filled in the interval opening; and the gate plug is positioned at the top of the gate structure of the gate contact region and is in contact with the gate structure. According to the embodiment of the invention, the source-drain contact structure is an integrated structure, and the electrical connection performance between the source-drain plug and the source-drain contact layer is improved.

The invention discloses a lossy image compression transmission method and system. The encoding process is: S1, attribute the colors that meet the range into one color; S2, mark the first frame as an I frame, obtain the color type value, and mark it as the basis Color value; S3, calculate the difference, when the difference is greater than the basic color value, then mark the next frame as an I frame, otherwise it is an F frame; S5, analyze the I and F frames to obtain color distribution information and establish a color list, the color list is greater than threshold, execute S6, otherwise S7; S6, reduce color types and re-execute S1; S7, establish compression code according to the color distribution information and output it. The system is used to execute the method. The present invention reduces the difficulty of forming the color list by distinguishing the type of the frame, improves the compression loss rate through the limitation of the color list, reduces the difficulty of data transmission, can reasonably complete the compression of the image and can reduce the difficulty of data transmission according to the requirements, and is beneficial in Used in IoT systems with low processing power.

The invention provides a battery cathode material. The battery cathode material comprises sulfur particles, a conductive additive and graphene, wherein the sulfur particles are loaded on the surface of the conductive additive; the conductive additive and the sulfur particles are wrapped into the graphene; and the conductive additive comprises the following constituents based on weight: 1-10 parts of Pb3O4 and 25-50 parts of Beta-PbO2. By the battery cathode material, the content of lead dioxide is increased, the polar plate formation difficulty is reduced, and the capacity of a polar plate is improved; with the addition of the Beta-PbO2, the capacity of a battery can be improved, and meanwhile, the charging and discharging voltage of the battery is increased slightly; and by adjusting the proportion of the Pb3O4 and Beta-PbO2, the strength of the polar plate, the charging and discharging voltage at an early stage, the charging and discharging voltage at a post stage, the cyclic post-stage capacity and the like are improved to an ideal level.

The invention discloses a manufacturing method of an infrared detector. The manufacturing method comprises: forming a detector mesa on an N-type substrate, and the detector mesa includes N-type InAsP / InAsSb superstructures formed sequentially on the N-type substrate. Lattice absorption layer, InPSb barrier layer and N-type InAsP / InAsSb superlattice contact layer; the first electrode is formed on the N-type InAsP / InAsSb superlattice contact layer on the detector table, and formed on the N-type substrate A second electrode corresponding to the detector mesa. The invention also discloses an infrared detector manufactured by the above manufacturing method. The invention solves the problem that it is difficult to form a heterojunction structure in the manufacturing process of the infrared detector.

A formation method of a contact plug comprises the steps of providing a substrate; forming an interlayer dielectric layer on the substrate; forming a high K dielectric layer on the interlayer dielectric layer; etching the high K dielectric layer and the interlayer dielectric layer orderly until the substrate is exposed to form a contact hole; continuously etching the high K dielectric layer along the contact hole until the diameter of the contact hole located at the high K dielectric layer is increased; adopting a conductive material to fill the contact hole. The formation method of the contact plug enables the formation difficulty of the contact plug to be reduced and also the quality of the formed contact plug to be improved.

Disclosed in the invention is a semiconductor device comprising a semiconductor substrate, a semiconductor drift region, base electrode regions, source regions, a grid dielectric layer, a grid electrode, metal pre dielectric layers, and a second electrode. To be specific, a first electrode is formed at one side of the semiconductor substrate. The semiconductor drift region is formed by a first drift region, a second drift region, and a third drift region; and the first drift region, the second drift region, and the third drift region are stacked at the other side of the semiconductor substrate upwardly in sequence. The base electrode regions are formed inside the third drift region. The source regions are formed inside the base electrode region. The grid dielectric layer is formed on the third drift region and is located between the two base electrode regions. The grid electrode is formed on the grid dielectric layer. The metal pre dielectric layers are formed around the grid electrode and at the top of the third drift region except the portion between the two source regions. The second electrode is formed on the grid electrode, the metal pre dielectric layers, and the third drift region between the two source regions. In addition, the invention also discloses a forming method of the semiconductor device. Therefore, the charge balance capability of the super junction drift region can be effectively improved.