A 11t TFET SRAM Cell Circuit Structure with Low Power Consumption and High Write Margin

Abstract

The invention discloses a 11T TFET SRAM unit circuit structure with low power consumption and high write margin, which includes nine NTFET transistors and two PTFET transistors, the nine NTFET transistors are sequentially denoted as N1-N9, and the two PTFET transistors are denoted sequentially For P1 and P2, VDD is connected to the drain of the NTFET transistor N4, and VDD is also electrically connected to the sources of the PTFET transistor P1 and the PTFET transistor P2; the drain of the PTFET transistor P1 is connected to the drain of the NTFET transistor N1 and the NTFET transistor N5 The source of the PTFET transistor N7, the drain of the NTFET transistor N7, the gate of the PTFET transistor P2, and the gate of the NTFET transistor N2 are electrically connected. The circuit structure not only solves the problem of poor structure retention and read ability of the traditional TFET SRAM unit, but also improves the stability of the SRAM unit.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a 11T TFETSRAM unit circuit structure with low power consumption and high write margin. Background technique [0002] With the continuous improvement of MOS manufacturing process, the device size is also reduced, which promotes the vigorous development and technological progress of the integrated circuit industry. However, MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) is an important part of digital integrated circuits and analog integrated circuits. Due to the continuous reduction of its feature size, the threshold voltage gradually increases, and the off-state current deteriorates day by day, making the static leakage current of the circuit And static power consumption is seriously increased, so people's demand for low-power devices is increasingly urgent. In addition, the sub-threshold swing of MOSFET at room temperature is limited by the thermoelectr...

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Problems solved by technology

For NTFET, when the source voltage is higher than the drain voltage, there will always be a p-i-n forward bias current that is not controlled by the gate, which will affect its static noise margin and read noise margin when it is applied in an SRAM circuit. Accuracy and static power consumption have a severe impact on the

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