16 results about "Dielectric capacitance" patented technology

This invention discloses a low-voltage pre-calibrated single-current sampling DBD equivalent parameter measurement method and system. Addressing the core shortcomings of existing DBD parameter measurement technologies, such as complex hardware, significant safety hazards from high-voltage sampling, inherent errors introduced by measurement capacitors, and imprecise derivations of single-current sampling schemes, this invention employs a two-step method to achieve full parameter measurement using only single-channel current sampling: First, pre-calibration is performed under low-voltage, undischarged conditions to obtain the DBD series equivalent capacitance and the initial phase of the excitation voltage; then, the circuit current is sampled under normal discharge conditions, and the discharge / undischarge interval is accurately divided using the sliding window variance method. Based on the data from the undischarged interval, a complete excitation voltage waveform is fitted, and finally, all equivalent parameters, including dielectric capacitance, air gap capacitance, discharge sustaining voltage, and discharge power, are calculated. This invention eliminates the need for additional hardware such as high-voltage probes and measurement capacitors, enabling online measurement of equivalent parameters.

The invention provides a semiconductor device, a preparation method, an integrated circuit and electronic equipment, and the semiconductor device comprises a channel layer, a dielectric layer above the channel layer, a source region and a drain region which are located at the two opposite sides of the channel layer and the dielectric layer, and a metal gate structure. The dielectric layer comprises an annular first dielectric region and second dielectric regions located on the two opposite sides of the first dielectric region, and the metal gate structure is wrapped in the first dielectric region. In the preparation process, a plurality of sub-sacrificial layers with different Ge material concentrations are stacked to form a sacrificial laminated layer, and the positions of the sub-sacrificial layers with different Ge material concentrations are controlled to control the etching rates of different positions on the periphery of the sacrificial laminated layer, so that the shape of the metal gate structure is controlled, and the metal gate structure is formed. The risk of short circuit between the metal gate structure and the source electrode region / drain electrode region at the top surface and the bottom surface is reduced, the dielectric capacitance of the second dielectric region at the position is effectively reduced, and the delay of an RC signal from the metal gate structure to the source electrode region / drain electrode region can be reduced.

A semiconductor device, a manufacturing method, an integrated circuit, and an electronic device, which are used for reducing the dielectric capacitance of semiconductor devices. The semiconductor device comprises a channel layer, a dielectric layer located on the channel layer, a source area and a drain area located on two opposite sides of the channel layer and the dielectric layer, and a first metal gate structure; the dielectric layer comprises an annular first dielectric area and a second dielectric area located on two opposite sides of the first dielectric area; a cavity in contact with the first dielectric area is formed in the second dielectric area; and the first metal gate structure is wrapped in the first dielectric area. By providing, in the second dielectric area, the cavity in contact with the first dielectric area, the low dielectric constant of air in the cavity can be utilized to reduce the overall dielectric constant of the second dielectric area, so as to reduce the dielectric capacitance of the second dielectric area, thereby reducing the RC signal delay from the first metal gate structure to the source area / drain area, and improving the switching performance of the semiconductor device.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication. In an example, an integrated circuit structure includes a single dielectric layer above a substrate. A plurality of conductive lines is in an upper portion of the single dielectric layer above a lower portion of the single dielectric layer. A carbon dopant region is in the upper portion of the single dielectric layer, the carbon dopant region between adjacent ones of the plurality of conductive lines.

The application provides a method for reducing a flipping electric field of a ferroelectric material, which can be applied to the technical fields of ferroelectric materials and semiconductor devices, and comprises the following steps: arranging a top electrode and a bottom electrode on opposite sides of the ferroelectric material respectively to form a ferroelectric capacitor; and connecting the ferroelectric capacitor and a dielectric capacitor in series to form a ferroelectric-dielectric system, so as to inhibit the ferroelectricity of the ferroelectric material and reduce the flipping electric field of the ferroelectric material. The reduction degree of the flipping electric field of the ferroelectric material is related to the capacitance value of the dielectric capacitor. The method for reducing the flipping electric field of the ferroelectric material by connecting the ferroelectric body and the dielectric body in series breaks through the limitation of the traditional scheme and has the characteristics of simple principle, non-destructiveness, small implementation difficulty and large regulation range.

The application provides a pipe defect risk early warning method based on industrial big data, and belongs to the technical field of early warning. The pipe defect risk early warning method based on industrial big data comprises the following steps: S1: collecting a multi-section heating current sequence of a pipe extruder barrel and a circumferential dielectric capacitance distribution sequence of a cooling and demolding section; S2: performing smoothing processing on the multi-section heating current sequence, extracting a thermal pulsation range difference representing melt plasticization fluctuation, and extracting a dielectric divergence feature representing pipe internal compactness abnormality based on the circumferential dielectric capacitance distribution sequence; S3: time window registering the thermal pulsation range difference and the dielectric divergence feature, and constructing a plasticization-dielectric coupling scatter point set reflecting pipe forming quality in a two-dimensional space; and S4: periodically calculating a minimum circumscribed polygon area of the plasticization-dielectric coupling scatter point set, and defining an expansion slope of the area with time as a pipe degradation incubation index.

There is provided a filter device including an acoustic resonator, the acoustic resonator having: a substrate; a piezoelectric layer coupled to the substrate through one or more intermediate layers; and a conductor pattern on a surface of the piezoelectric layer, the conductor pattern including a pair of bus bars having a plurality of interdigitated fingers extending therefrom to form an interdigital transducer (IDT). The filter device also includes a dielectric capacitor electrically coupled in series to the acoustic resonator. The dielectric capacitor includes a dielectric layer on a surface of a first bus bar of the pair of bus bars, and at least one metal layer on a surface of the dielectric layer such that the dielectric layer is between the first bus bar and the at least one metal layer to form the dielectric capacitor.

The invention provides a high-voltage cable insulation state detection method and device and electronic equipment, and the method comprises the steps: obtaining the structure parameters of a to-be-detected high-voltage cable, the to-be-detected high-voltage cable at least comprises an insulation layer and an insulation defect, the insulation defect is located in the insulation layer, and the structure parameters at least comprise the radius of the insulation defect; a finite element simulation model of the to-be-detected high-voltage cable is constructed according to the structure parameters, defect capacitance of insulation defects and insulation medium capacitance of an insulation layer are calculated according to the finite element simulation model, and the finite element simulation model is used for simulating the structure and the electric field of the to-be-detected high-voltage cable; and determining the real discharge capacity of the to-be-detected high-voltage cable according to the ratio of the defect capacitance to the insulating medium capacitance, and determining that the to-be-detected high-voltage cable is in a non-insulating state under the condition that the real discharge capacity is greater than a preset threshold value. According to the application, the problem that the insulation state of the cable cannot be accurately judged in the prior art is solved, and the effect of accurately judging the insulation state of the cable is achieved.

This invention discloses a holmium-doped copper ferrite multiferroic ceramic and its preparation method. The holmium-doped copper ferrite multiferroic ceramic is made from Cu... 1‑x Ho x FeO2 represents a ceramic material prepared using a sol-gel self-propagating combustion method, where 0 < x ≤ 0.08, with copper nitrate trihydrate, ferric nitrate nonahydrate, holmium nitrate pentahydrate, citric acid monohydrate, and ethylene glycol as raw materials. This ceramic material possesses a single-phase structure, room-temperature giant dielectric properties, and low-temperature magnetism. Furthermore, by changing Ho... 3+ The amount of doping can adjust the giant dielectric properties and magnetism of the material; its preparation process is simple, requiring no pre-firing, with low sintering temperature, short sintering time, low cost, and is environmentally friendly and harmless, and has broad application prospects in fields such as high dielectric capacitors, information storage, spintronic devices, and magnetoelectric sensors.

The application belongs to the technical field of flexible electronic dielectric materials, and particularly relates to a rare earth doped layered perovskite flexible dielectric energy storage film and a preparation method thereof. 2+ The insulating layer and the (A n‑1 B n O 3n+1 ) 2‑ The perovskite layers are alternately stacked along the c-axis direction, and the doping ion Pr 3+ exists in the (Bi2O2) 2+ The insulating layer and the (A n‑1 B n O 3n+1 ) 2‑ The perovskite layers, the film is deposited on a flexible fluorophlogopite substrate, is prepared by using a chemical solution deposition method, and is obtained by sequentially performing precursor preparation, spin coating, segmented heat treatment, cycle film preparation and high-temperature crystallization. Relying on the double-dipole synergistic effect, the film synchronously improves the polarization intensity and the breakdown field strength, and the energy density and the charge and discharge efficiency are far superior to those of existing materials. The film has excellent bending cycle and charge and discharge cycle stability, can stably work in a wide frequency and wide temperature range, and is suitable for use in dielectric capacitors in flexible intelligent systems such as wearable electronics and flexible robots.

The invention relates to a copper calcium titanate nanoflower and a preparation method thereof, and belongs to the field of high-dielectric-constant electronic ceramic materials. The size of the copper calcium titanate nanoflower is 100-500 nm, the shape of the copper calcium titanate nanoflower is petal-shaped, and the dielectric constant of the copper calcium titanate nanoflower at 100 Hz is 2 * 10 < 4 >-8 * 10 < 5 >. The preparation scheme of the copper calcium titanate nanoflower comprises the following steps: firstly synthesizing titanium dioxide nanoflower from tetrabutyl titanate and hydrochloric acid through a hydrothermal method; and then synthesizing the copper calcium titanate nanoflower by a hydrothermal method by taking the titanium dioxide nanoflower as a template, copper nitrate trihydrate and calcium nitrate tetrahydrate as raw materials and a phenolic compound as an additive. The copper calcium titanate nanoflower prepared by the method has excellent dielectric properties and petal-shaped morphology, can be widely applied to high-dielectric composite materials, and can also be applied to the field of dielectric capacitors. The preparation process of the copper calcium titanate nanoflower is simple, convenient and easy to implement, low in cost and suitable for industrial continuous and mass production, and the prepared copper calcium titanate nanoflower is excellent in performance, has petal-shaped morphology and can be used for dielectric composite materials.

The application relates to the technical field of micro-electro-mechanical system sensors, in particular to a multi-modal gas humidity sensor and a control method and a preparation method thereof, the sensor comprising a monolithic integrated sensing unit, a multi-modal switching switch matrix, a driving and detecting circuit, a measurement and control system, a wireless communication module and an upper computer, the output end of the driving and detecting circuit is electrically connected with the signal input end of the measurement and control system, the signal output end of the monolithic integrated sensing unit is electrically connected with the input end of the multi-modal switching switch matrix, and the output end of the multi-modal switching switch matrix is electrically connected with the input end of the driving and detecting circuit, the CMUT and the IDE monolithic integration are realized through wafer bonding and single peeling process, the switching matrix is used to realize three detection mode switching and feature slope anti-wet interference discrimination, the monolithic integrated sensing unit is constructed by connecting the CMUT and the IDE in parallel, the collaborative response of the mass load effect and the dielectric capacitance effect is realized, and the detection sensitivity is improved.

Novel dielectric capacitor devices include an electrically conductive porous scaffold forming a first conductor, a conformal thin dielectric uniformly coating the pores, and a metal or alloy which fills the conformal dielectric coated pores of the scaffold forming a second conductor. This structure's design provides high surface area for high energy storage and capacitance density as well as high thermal conductivity. The metal or alloy can be a liquid metal and flowed within the device to change the electrical or mechanical properties of the device.

This utility model discloses a dielectric capacitance sensor that facilitates welding positioning, relating to the field of dielectric capacitance sensor welding technology. Its key technical features include a tooling base plate and a welding placement plate. Two limiting rods are fixedly connected to the upper end of the tooling base plate, and a support seat is slidably connected to each limiting rod. The welding placement plate has multiple placement slots at its upper end, each containing a mounting mechanism for installing sensors. This utility model, by setting up the mounting mechanism, enables the individual and rapid removal of failed welding sensors, avoiding damage to qualified sensors or delays in the re-welding process due to batch removal. Simultaneously, the cooperation between the positioning column and the sliding support seat allows for the batch removal of qualified sensors, balancing operational flexibility and production efficiency, effectively improving the stability and convenience of dielectric capacitance sensor welding operations.

The invention discloses a semiconductor device, a preparation method, an integrated circuit and electronic equipment, which are used for reducing dielectric capacitance of the semiconductor device. The semiconductor device comprises a channel layer, a dielectric layer above the channel layer, a source region, a drain region and a first metal gate structure, the source region and the drain region are located on the two opposite sides of the channel layer and the dielectric layer, and the dielectric layer comprises an annular first dielectric region and second dielectric regions located on the two opposite sides of the first dielectric region. The second dielectric region is provided with a cavity in contact with the first dielectric region, and the first metal gate structure is wrapped in the first dielectric region. By forming the cavity in contact with the first dielectric region in the second dielectric region, the overall dielectric constant of the second dielectric region can be reduced by using the low dielectric constant of air in the cavity, so that the dielectric capacitance of the second dielectric region is reduced, the RC signal time delay from the first metal gate structure to the source region / drain region is reduced, and the switching performance of the semiconductor device is improved.

Wireless-enabled loudspeaker includes a capacitive touch user interface. The loudspeaker may comprise at least one electroacoustic transducer, a processor in communication with the at least one electroacoustic transducer, and an exterior surface comprising a capacitive touch user interface that allows a user to control operation of the loudspeaker. The exterior surface acts a dielectric for the capacitive touch user interface. The loudspeaker may comprise a wireless transceiver circuit for receiving and transmitting wireless communication signals via a wireless network. The wireless transceiver circuit may receive wirelessly audio content from streaming audio content servers that are connected to the Internet. The capacitive touch user interface comprises a plurality of capacitive sense electrodes.