Efficient decoder architecture suitable for 5G LDPC code

Abstract

The invention discloses a decoder architecture which is universal for 5G LDPC codes and is high in throughput rate and low in complexity for the first time. Firstly, by utilizing partial orthogonalityof a 5G LDPC code base matrix, the number of clock cycles is reduced by adopting a layer merging technology, and meanwhile, the area consumption of a check information memory is reduced. Secondly, because the line weight of the 5G LDPC is very irregular, a distributed storage structure is adopted to reduce the consumption of storage resources. And finally, in order to solve the problems of high delay and high complexity caused by large-scale reading and writing into the internet, a shifting structure is adopted to realize the soft message memory, so that the input and output number of the internet is greatly reduced. In addition, information rearrangement is applied to the internet to optimize the internal architecture of the internet. Compared with the conventional design, the decoder disclosed by the invention has the advantages that the area is greatly reduced, a higher throughput rate can be provided, and the throughput rate-area ratio is increased to 2.68 times of the original throughput rate-area ratio.

Description

[0001] Technical field [0002] The present invention relates to the decoder architecture design in the technical field of communication coding, especially for the high-throughput and low-complexity decoder architecture suitable for 5G LDPC codes. Background technique [0003] Error correcting codes are very important components in modern communication systems. In the latest 5G communication standard, LDPC codes are adopted as channel coding schemes due to their superior error correction performance and relatively low decoding complexity. Different from conventional LDPC codes, 5G LDPC codes need to be able to meet code rate compatibility in order to support hybrid automatic repeat request (HARQ). Therefore, its basic matrix is ​​a concatenation of a high code rate LDPC code matrix and a low density generator matrix (LDGM). The row and column weights of 5G LDPC codes are extremely irregular, and there are great differences between the row weights of each check node and the c...

AI Technical Summary

Problems solved by technology

Although the decoding architecture design of LDPC has been extensively studied, however, there is currently no decoder specifically designed for 5G LDPC codes

Considering its structural particularity, if a general-purpose decoding architecture is used, it will cause a lot of waste of resources and unsatisfactory throughput

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