Test set reordering method and device based on estimated test performance of testable area

A technology for testing performance and test sets, applied in the direction of electronic circuit testing, automated testing systems, etc., can solve problems such as low test performance, and achieve the effect of reducing test time, simple method, and shortening fault detection time

Active Publication Date: 2020-03-13
陕西久润达电子科技有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The technical problem to be solved by the present invention is to provide a test set reordering method and device for estimating test performance based on the testable area, so as to solve the problem of low test performance of the test set as a whole

Method used

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  • Test set reordering method and device based on estimated test performance of testable area
  • Test set reordering method and device based on estimated test performance of testable area
  • Test set reordering method and device based on estimated test performance of testable area

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Embodiment 1

[0038] First of all, it needs to be explained that, regardless of the design defects of the integrated circuit itself or the loopholes in the manufacturing process, the occurrence of failures is a small probability event, the occurrence of failures is relatively independent, and the failure rate is relatively stable, that is, the occurrence of failures obeys Poisson distribution. Assume that an existing integrated circuit X contains n logic gates. In the standard cell library (in the integrated circuit manufacturing process, different manufacturing processes use different standard cell libraries, and the length, length, and Width.) The length and width of each type of logic gate are known. In the actual test, the test vectors have the characteristics that they can be merged and the order cannot be adjusted.

[0039] Such as figure 1 , a test set reordering method based on estimating test performance, including the following steps:

[0040] S1. Generate a test set and simulat...

Embodiment 2

[0063] A sorting device for a test set reordering method based on estimating test performance, comprising:

[0064] The test set module is used to generate test sets and simulate tests;

[0065] Also includes the following steps:

[0066] S11, using an automatic test generation algorithm to make the integrated circuit X generate a test set V of the Y test type 1 ,V 2 ,...,V i ,...,V n , including input sequence and output sequence; because there are n types of faults to be tested in actual testing, it is necessary to generate n types of test sets;

[0067] In this embodiment, the automatic test generation algorithm is an existing technology, and will not be described in detail here.

[0068] S12. Analyze the logic gate structure inside the integrated circuit X, and build a simulation environment to restore the logic gate structure through programming to perform fault simulation testing;

[0069] When testing, sequentially use the test set V 1 ,V 2 ,...,V i ,...,V m E...

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Abstract

The invention relates to a test set reordering method based on estimated test performance. The method comprises the following steps: S1, generating a test set and performing simulation test; S2, estimating the fault test performance of test vectors in the test set; and S3, reordering the test set after estimation to obtain a new test set. The invention further discloses a test set reordering device based on estimated test performance. The test vectors are reordered according to the test performance, and the reordered test vectors are used for testing. Therefore, the test time of a fault circuit can be shortened, and the test efficiency can be improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuit testing, in particular to a test set reordering method and device for estimating test performance based on a testable area. Background technique [0002] With the continuous improvement of integrated circuit manufacturing technology and the rapid increase of circuit integration, the number of transistors integrated on a single chip is increasing exponentially, and the corresponding test data volume will be even larger. Automatic test equipment (Automatic Test Equipment, ATE) is used to detect the integrity of integrated circuit functions, and is the final process of integrated circuit manufacturing to ensure the quality of integrated circuit manufacturing. As the complexity of circuit structures increases, chip manufacturers spend more and more on chip testing. For this reason, reducing the test cost has become an important task; the cost of automated test equipment ATE is expensive, a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28
CPCG01R31/2834
Inventor 詹文法陶鹏程蔡雪原邵志伟彭勇张振林丁文祥彭登辉华铭都奕
Owner 陕西久润达电子科技有限公司
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