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Method for forming metal silicide

A metal silicide, metal film layer technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems affecting device quality, discontinuity, large difference in resistance value of cobalt silicide, etc., to improve resistance Uniformity and quality-improving effects

Pending Publication Date: 2020-03-24
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Claims
  • Application Information

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Problems solved by technology

[0004] The resistance uniformity of the cobalt silicide formed above is poor, such as figure 1 As shown, for example, there is a discontinuous silicide defect a, which causes a large difference in the resistance value of the cobalt silicide formed on some regions, which affects the quality of the subsequently formed device

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  • Method for forming metal silicide

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Embodiment Construction

[0031] The core idea of ​​the present invention is to provide a method for forming a metal silicide, comprising the following steps: providing a semiconductor substrate on which a natural oxide film is formed; etching and removing the natural oxide film, and The etching stops on the semiconductor substrate, and the etching time is the time required to etch the natural oxide film with a thickness c, and the thickness c satisfies the formula: c=a+b, where a is The film thickness of the natural oxide film, b is a variable; forming a metal film layer and an additive film layer on the semiconductor substrate, and performing the first thermal annealing process to form an initial metal silicide; removing the unformed initial metal silicide the metal film layer and the additive film layer; and performing a second thermal annealing process to form a metal silicide. The present invention reduces the number of discontinuous silicide defects formed during etching by adjusting the time for...

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Abstract

The invention provides a method for forming metal silicide, which comprises the following steps: providing a semiconductor substrate, and forming a natural oxide film on the semiconductor substrate; removing the natural oxide film through etching, stopping etching on the semiconductor substrate, the etching time being the time needed for etching the natural oxide film with the thickness c, the thickness c meeting the formula of c = a + b, a being the film thickness of the natural oxide film, and b being a variable; forming a metal film layer and an additive film layer on the semiconductor substrate, and executing a first thermal annealing process to form an initial metal silicide; removing the metal film layer and the additive film layer on which the initial metal silicide is not formed; and performing a second thermal annealing process. According to the method, the number of discontinuous silicide defects formed in etching is reduced by adjusting the time for removing the natural oxide film through etching, so that the resistance uniformity of the metal silicide is improved, the quality of a subsequently formed device is improved, and the resistance value of the region where the formed metal silicide is located can be adjusted.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing technology, in particular to a method for forming a metal silicide. Background technique [0002] With the continuous development of integrated circuits, the silicide process has been introduced into the manufacturing process. And from the initial polycide (silicide on polysilicon) process to today's salicide (silicide) process. In the 0.18μm and 0.13μm processes, cobalt silicide (CoSi 2 ). It has the following advantages: low resistivity, good thermal stability, and the temperature of silicide formation will not increase with the reduction of line width. [0003] At present, there are roughly three types of methods for preparing silicides: one is to deposit Co (cobalt) directly on the surface of silicon by PVD (Physical Vapor Deposition), and the second is to use a double-layer metal, the main body is also Co, and PVD first under the Co metal Deposit a thin layer of T...

Claims

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Application Information

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IPC IPC(8): H01L21/311H01L21/285H01L21/768
CPCH01L21/31116H01L21/2855H01L21/76895
Inventor 曹启鹏陈宏王卉
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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