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Silicon-based quadrangular frustum pyramid-shaped micro through hole array, preparation method and application thereof

A quadrangular pyramid-shaped, miniature technology, applied in the field of material processing, can solve the problems of accumulated errors and low efficiency, and achieve the effects of high processing efficiency, precise and controllable relative position and hole shape

Active Publication Date: 2020-03-31
THE NAT CENT FOR NANOSCI & TECH NCNST OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, laser drilling is a serial operation. Generally, pulsed laser is used to ablate the holes by thermal effect. For large-scale hole array processing, its efficiency is low.
In addition, the holes processed by it are usually conical, and more importantly, the accuracy of the relative position between holes is completely guaranteed by the feed mechanism, which is prone to cumulative errors in the processing of hole arrays

Method used

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  • Silicon-based quadrangular frustum pyramid-shaped micro through hole array, preparation method and application thereof
  • Silicon-based quadrangular frustum pyramid-shaped micro through hole array, preparation method and application thereof
  • Silicon-based quadrangular frustum pyramid-shaped micro through hole array, preparation method and application thereof

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Effect test

Embodiment 1

[0068] This embodiment is used to illustrate the preparation method of the tetragonal truss micro-via array of the present invention.

[0069] (1) Make the mask plate Use AutoCAD software to draw the required graphics array, and then send the file to Shenzhen Meijing Micro Optoelectronics Co., Ltd., which will make the mask plate.

[0070] The mask plate produced is a five-inch chrome plate, the graphic array is a rectangle, the length of the rectangle is 30 μm, the width is 8 μm, the distance between each two rectangles is 60 μm, and 10,000 rectangles are distributed in an area of ​​14mm×14mm, each There are 24 rectangular arrays spread across the chrome board.

[0071] (2) Choose a double-sided polished silicon wafer substrate

[0072] The type of silicon wafer is N-type, the crystal orientation is (100), the dopant is phosphorus, the diameter is 100 mm, and the thickness is 200 μm.

[0073] (3) One side of the silicon wafer is coated with glue, exposed and developed

[0...

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Abstract

The invention provides a silicon-based quadrangular frustum pyramid-shaped micro through hole array, a preparation method and application thereof. Different from a conventional silicon-based miniaturethrough hole which needs serial operation of a laser drilling technology and laser scanning according to a track, the method has the advantages that hole arrays are machined in parallel through photoetching and dry etching processes, all holes in the arrays can be machined at the same time, the machining efficiency is high, and the relative positions and hole patterns among the holes are accurateand controllable.

Description

technical field [0001] The invention belongs to the field of material processing, and in particular relates to a silicon-based quadrangular truss micro-through-hole array, a preparation method and application thereof. Background technique [0002] Laser drilling is the earliest practical laser processing technology, and has been widely used in various material systems. Micro-vias on silicon substrates refer to the pore diameters penetrating silicon wafers on the order of microns. With higher integration, micro-vias are more useful in conducting signals. Silicon-based micro-vias obtained by laser drilling technology have been widely used in various fields such as microelectronic integration, optoelectronic integration, solar cells, and perforated electrodes in the semiconductor field. However, laser drilling is a serial operation. Generally, pulsed laser is used to ablate holes by thermal effect. For large-scale hole array processing, its efficiency is low. In addition, th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): B81C1/00
CPCB81C1/005B81C1/00531B81C2201/0115B81C2201/0132
Inventor 蒋兴宇尹佳祥张伟
Owner THE NAT CENT FOR NANOSCI & TECH NCNST OF CHINA
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