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Multi-patterning method and method of forming memory

A multi-patterning and memory technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of lithographic process precision limitation, inability to flexibly adjust the graphic size, etc., and achieve the effect of small-sized graphic preparation

Active Publication Date: 2021-12-24
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] The purpose of the present invention is to provide a multi-patterning method to solve the problem that the existing patterning process is easily limited by the precision of the photolithography process and cannot flexibly adjust the pattern size

Method used

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  • Multi-patterning method and method of forming memory

Examples

Experimental program
Comparison scheme
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Embodiment 1

[0073] figure 1 It is a schematic flow chart of the multiple graphics method in Embodiment 1 of the present invention, Figure 2a ~ Figure 2f It is a schematic structural diagram of the multi-patterning method in the first embodiment of the present invention during its patterning process, and each step in the first embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

[0074] In step S110, specifically refer to Figure 2a As shown, a substrate 100 is provided, on which a pattern transfer layer 110 and a first mask material layer 120 are sequentially formed. In the subsequent process, the pattern to be transferred is defined on the pattern transfer layer 110 , and the defined pattern is further transferred into the pattern transfer layer 110 .

[0075] In step S120, continue to refer to Figure 2a As shown, a first photoresist layer 130 is formed on the first mask material layer 120 , and a plurality of first patt...

Embodiment 2

[0093] image 3 It is a schematic flow chart of the forming method of the memory in Embodiment 2 of the present invention, Figure 4a ~ Figure 4g It is a structural schematic diagram of the memory in the second embodiment of the present invention during its formation process. Each step in this embodiment will be described in detail below with reference to the accompanying drawings.

[0094] In step S210, specifically refer to Figure 4a As shown, a substrate 200 is provided, and a plurality of active regions AA are defined on the substrate 200, node contact areas NCA are respectively provided on opposite ends of the active regions AA, and on the substrate A dielectric layer 270 and a first mask material layer 220 are also sequentially formed on the bottom 100 .

[0095] In the subsequent process, the first mask material layer 220 is used to define a desired pattern on the dielectric layer 270 , and the defined pattern is transferred to the dielectric layer 270 . Further, t...

Embodiment 3

[0126] The difference from Embodiment 2 is that in this embodiment, after forming the dielectric layer and before forming the first mask material layer, it further includes: performing a planarization process on the dielectric layer to reduce the dielectric layer layer height.

[0127] Figure 5a It is a structural schematic diagram of the method for forming the memory in Embodiment 3 of the present invention after the dielectric layer is planarized. like Figure 5a As shown, in this embodiment, the dielectric layer 270 is planarized, and planarized to the cover layer of the bit line BL (that is, after the planarization process, the position of the top surface of the dielectric layer 270 is, for example, between the top surface location and the bottom surface location of the capping layer of the bit line BL). At this time, on the basis of reducing the height of the dielectric layer 270 , it is also possible to prevent the conductive layer in the bit line BL from being expos...

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Abstract

The invention provides a multi-patterning method and a method for forming a memory. The size of the first pattern is adjusted by using a chemical shrinkage agent, so that the gap between the mask patterns copied into the first mask layer is smaller, and based on this, the second mask layer can be filled in the gap The filling part has a smaller size, and at the same time, based on the different etching rates of the first mask layer and the second mask layer, it can be ensured that part of the filling part remains when removing the exposed covering part and mask pattern , to form the first transfer graph and the second transfer graph respectively. It can be seen that, according to the multi-patterning method provided by the present invention, patterns with smaller sizes can still be defined under the limitation of the precision of the existing photolithography process.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a multi-patterning method and a method for forming a memory. Background technique [0002] With the continuous progress of semiconductor technology, the process nodes of semiconductor devices are continuously reduced. However, due to the limitation of the precision of the existing lithography process, it is impossible to directly prepare finer patterns with the existing lithography process, and it is also difficult to flexibly adjust the size of the pattern, so that it cannot meet the continuous reduction of semiconductor devices. Feature size (CriticalDimension, referred to as CD) requirements. Contents of the invention [0003] The purpose of the present invention is to provide a multi-patterning method to solve the problem that the existing patterning process is easily limited by the precision of the photolithography process and cannot flexibly adjust the pattern siz...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/027H01L21/033H01L21/8239
CPCH01L21/0274H01L21/0332H01L21/0338H01L21/0337H01L21/0335H10B99/00
Inventor 不公告发明人
Owner CHANGXIN MEMORY TECH INC
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