Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Multi-patterning method and memory forming method

A multi-patterning and memory technology, used in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of lithography process accuracy limitations, inability to flexibly adjust the pattern size, etc., and achieve the effect of small-sized pattern preparation

Active Publication Date: 2020-04-03
CHANGXIN MEMORY TECH INC
View PDF7 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to provide a multi-patterning method to solve the problem that the existing patterning process is easily limited by the precision of the photolithography process and cannot flexibly adjust the pattern size

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Multi-patterning method and memory forming method
  • Multi-patterning method and memory forming method
  • Multi-patterning method and memory forming method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0073] figure 1 It is a schematic flow chart of the multiple graphics method in Embodiment 1 of the present invention, Figure 2a ~ Figure 2f It is a schematic structural diagram of the multi-patterning method in the first embodiment of the present invention during its patterning process, and each step in the first embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

[0074] In step S110, specifically refer to Figure 2a As shown, a substrate 100 is provided, on which a pattern transfer layer 110 and a first mask material layer 120 are sequentially formed. In the subsequent process, the pattern to be transferred is defined on the pattern transfer layer 110 , and the defined pattern is further transferred into the pattern transfer layer 110 .

[0075] In step S120, continue to refer to Figure 2a As shown, a first photoresist layer 130 is formed on the first mask material layer 120 , and a plurality of first patt...

Embodiment 2

[0093] image 3 It is a schematic flow chart of the forming method of the memory in Embodiment 2 of the present invention, Figure 4a ~ Figure 4g It is a structural schematic diagram of the memory in the second embodiment of the present invention during its formation process. Each step in this embodiment will be described in detail below with reference to the accompanying drawings.

[0094] In step S210, specifically refer to Figure 4a As shown, a substrate 200 is provided, and a plurality of active regions AA are defined on the substrate 200, node contact areas NCA are respectively provided on opposite ends of the active regions AA, and on the substrate A dielectric layer 270 and a first mask material layer 220 are also sequentially formed on the bottom 100 .

[0095] In the subsequent process, the first mask material layer 220 is used to define a desired pattern on the dielectric layer 270 , and the defined pattern is transferred to the dielectric layer 270 . Further, t...

Embodiment 3

[0126] The difference from Embodiment 2 is that in this embodiment, after forming the dielectric layer and before forming the first mask material layer, it further includes: performing a planarization process on the dielectric layer to reduce the dielectric layer layer height.

[0127] Figure 5a It is a structural schematic diagram of the method for forming the memory in Embodiment 3 of the present invention after the dielectric layer is planarized. like Figure 5a As shown, in this embodiment, the dielectric layer 270 is planarized, and planarized to the cover layer of the bit line BL (that is, after the planarization process, the position of the top surface of the dielectric layer 270 is, for example, between the top surface location and the bottom surface location of the capping layer of the bit line BL). At this time, on the basis of reducing the height of the dielectric layer 270 , it is also possible to prevent the conductive layer in the bit line BL from being expos...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a multi-patterning method and a memory forming method. The size of a first pattern is adjusted by using a chemical shrinkage reagent; therefore, the gap between the mask patterns copied into the first mask layer is relatively small; therefore, the filling part filling the gap in the second mask layer has a relatively small size; meanwhile, based on the fact that the first mask layer and the second mask layer have different etching rates, it can be ensured that when the covering part and the mask pattern are removed and exposed, part of the filling part is reserved so asto form a first transfer pattern and a second transfer pattern respectively. Therefore, according to the multi-patterning method provided by the invention, a pattern with a smaller size can still be defined under the precision limitation of the existing photoetching process.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a multi-patterning method and a method for forming a memory. Background technique [0002] With the continuous progress of semiconductor technology, the process nodes of semiconductor devices are continuously reduced. However, due to the limitation of the precision of the existing lithography process, it is impossible to directly prepare finer patterns with the existing lithography process, and it is also difficult to flexibly adjust the size of the pattern, so that it cannot meet the continuous reduction of semiconductor devices. Feature size (CriticalDimension, referred to as CD) requirements. Contents of the invention [0003] The purpose of the present invention is to provide a multi-patterning method to solve the problem that the existing patterning process is easily limited by the precision of the photolithography process and cannot flexibly adjust the pattern siz...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/027H01L21/033H01L21/8239H10B99/00
CPCH01L21/0274H01L21/0332H01L21/0338H01L21/0337H01L21/0335H10B99/00
Inventor 不公告发明人
Owner CHANGXIN MEMORY TECH INC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com