Period detection system adapting to FPGA local reconstruction

Abstract

The invention discloses a period detection system adapting to FPGA local reconstruction, and aims to provide a framework which facilitates function transplantation and efficiently utilizes hardware resources. According to the technical scheme, a platform control management module receives control information sent by a system bus through communication middleware, monitors the operation of whole platform software in real time according to the requirements of the system, and controls the reconstruction of a reconstruction area. The generated global and local bit stream files and other configuration data are placed on a Flash memory, control information issued by the system is analyzed, and a scheduling processing process is set based on a periodic reconstruction algorithm of a function priority. During reconstruction, corresponding local reconfiguration data in a detection period is sequentially read, the function Bit operation body is serially loaded to the ICAP configuration interface of the FPGA. After loading is completed, the current reconstruction function is operated, reconstruction loading of the function in the reconstruction area is achieved, and the requirement for periodictime division multiplexing of the function on a periodic detection system hardware platform is met.

Description

technical field [0001] The invention relates to a partial-reconfiguration (partial-reconfiguration) technology based on a field programmable gate array FPGA. According to the detection cycle set by the cycle detection system, the cycle detection system periodically reconfigures and runs each function to be tested on the detection device. In particular, it is a cycle detection system that can be time-divided and operated in a local area of ​​a programmable logic device FPGA. Background technique [0002] At present, the research on evolvable hardware technology is mainly oriented to circuit and fault-tolerant design. The circuit design mainly applies the idea of ​​the evolutionary algorithm to effectively solve the system optimization problem in the FPGA, and uses the embedded processor as the reconstruction control unit. The shortcomings of evolutionary hardware are overcome. In addition, the improvement of the traditional genetic algorithm and the reconfigurable implement...

AI Technical Summary

Problems solved by technology

As far as the current application of this technology is concerned, there are still some deficiencies in the current cycle detection system: 1. The cycle detection system lacks an architecture design that facilitates function transplantation and efficiently utilizes hardware resources

[0006] 2. For the deployment of functions within the detection cycle, there is no effective function allocation method

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