Clock buffer

Abstract

The present invention provides a clock buffer including a first circuit, a second circuit and an edge collector, wherein the first circuit is arranged to receive an input clock signal to generate a first clock signal, the second circuit is arranged to receive the input clock signal to generate a second clock signal, and the edge collector is arranged to generate an output clock signal by using a falling edge of the first clock signal and a rising edge of the second clock signal.

Description

technical field [0001] The present invention relates to the technical field of clock generation, and more particularly, to clock buffers. Background technique [0002] A traditional clock buffer is usually implemented by an inverter, and its N-type metal oxide semiconductor (NMOS) and P-type metal oxide semiconductor (PMOS) are usually designed to be larger to obtain better noise performance. However, due to the rise / fall time, both NMOS and PMOS are turned on for a long time, the quiescent current generated during this duration may dominate the power consumption of the clock signal and generate spurs to affect other circuits, where if NMOS and PMOS With larger size, the quiescent current is higher. In order to solve this problem, U.S. Patent US8,427,209 provides a delay circuit in front of the PMOS to control the conduction period of the PMOS to reduce power consumption. However, this method will shorten the duty cycle of the output clock signal, And the edges of the outp...

AI Technical Summary

Problems solved by technology

However, due to the rise / fall time, both NMOS and PMOS are turned on for a long time, the quiescent current generated during this duration may dominate the power consumption of the clock signal and generate spurs to affect other circuits, where if NMOS and PMOS With larger size, more quiescent current

In order to solve this problem, U.S. Patent US8,427,209 provides a delay circuit in front of the PMOS to control the conduction period of the PMOS to reduce power consumption. However, this method will shorten the duty cycle of the output clock signal, and the edges of the output clock signal may drift to worsen the phase noise

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