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Dynamic graph processing method based on FPGA

A processing method and technology for dynamic graphs, which are applied in electrical digital data processing, special data processing applications, architecture with a single central processing unit, etc. It solves the problems of memory bandwidth utilization and high memory access delay, so as to reduce redundant computing, reduce memory access delay, and speed up incremental propagation.

Active Publication Date: 2020-05-05
HUAZHONG UNIV OF SCI & TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Since the FPGA-based full dynamic graph method lacks the perception of dynamic graph structural changes, there are the following problems when processing dynamic graphs: (1) The graph iteration convergence speed is slow: the current FPGA-based dynamic graph full methods all use a synchronous model to Graph data performs iterative calculations, and the calculation results in the current iteration can only be used in the next iteration; therefore, the increment in each iteration can only be propagated in a single step along the edge, and the propagation speed is slow; (2) High memory access latency: In dynamic graph changes, increments are propagated along the path direction; however, current FPGA-based graph processing systems store graph data according to graph vertex numbers; the numbers of graph vertices on a path are usually randomly distributed, and they The location in the memory is discontinuous, so the spatial locality and time locality of the graph data are very poor, resulting in low memory access bandwidth utilization and high memory access delay; (3) Redundant calculation: in the process of dynamic graph processing, only The graph data affected by the increment needs to be incrementally calculated. However, in the existing FPGA-based dynamic graph full-scale method, a large amount of graph data that is not affected by the increment still participates in the calculation process, resulting in redundant calculations.

Method used

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  • Dynamic graph processing method based on FPGA

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Embodiment 1

[0039] This embodiment discloses an FPGA-based dynamic image processing system. Such as figure 1 As shown, the system at least includes a preprocessing module 100a and an FPGA processing module 200 . The preprocessing module 100a divides the graph image into at least one path unit. Before dividing the graph image into path units, the preprocessing module 100a will determine whether there is an increment between graph images of adjacent time stamps. If there is an increment between the image images of adjacent time stamps, the preprocessing module 100a divides the image images of the next time stamp into at least one path unit. Preferably, in the path unit, the incremental calculation of any graph vertex only depends on the preceding graph vertex of the arbitrary graph vertex.

[0040] Preferably, the preprocessing module 100a is configured to divide the image image in the following sub-steps:

[0041] S1: Traverse the graph image of the dynamic graph corresponding to the n...

Embodiment 2

[0056] It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not constitute a conflict with each other.

[0057] Preferably, the preprocessing module 100a can also be divided according to the following preprocessing sub-steps:

[0058]P1: The preprocessing module 100a can select at least one common node as the initial point for traversal, record the traversal path and mark the nodes with increments. For example the common nodes could be 1, 8, 10. When a common node traverses to another common node, the traversal ends. This method has the following advantages: 1. Simultaneous traversal can save the preprocessing time of the preprocessing module 100a; 2 path identification is faster, and common nodes generally have com...

Embodiment 3

[0062] In order to make the object, technical solution and advantages of the present invention clearer and easier to understand, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The FPGA-based dynamic graph processing method provided by the present invention includes a preprocessing step and an incremental calculation step, specifically as follows:

[0063] (1) The effect of the preprocessing module 100 is to obtain the path set in the latest image image according to the increment between two adjacent image images of the dynamic graph, including the following sub-steps:

[0064] (1.1) If the dynamic graph is processed for the first time, then use the graph partition method to divide the graph image into a set of paths and store them in the memory; otherwise, enter step (1.2);

[0065] (1.2) Each edge in the increment is loaded into the on-chip memory, and the path position in the old graph image wher...

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Abstract

The invention relates to a dynamic graph processing method based on an FPGA. The method comprises the steps that under the condition that increment exists between image mirror images of adjacent timestamps of a dynamic graph, a preprocessing module divides the image mirror image of the next timestamp into at least one path unit in the mode that increment calculation of any graph vertex only depends on a preorder graph vertex of the any graph vertex; the FPGA processing module stores the at least two path units in an on-chip memory directly connected with a thread according to a mode that eachthread unit can independently process the path unit; and the thread unit determines an increment value between adjacent timestamps of the vertex of the preorder graph under the condition that the state value of the vertex of the preorder graph is updated, and transmits the increment value to a subsequent graph vertex adjacent to the vertex of the preorder graph according to the transmission direction determined by the path unit so as to update the state value of the subsequent graph vertex.

Description

technical field [0001] The invention relates to the technical field of graph calculation for computer big data processing, in particular to an FPGA-based dynamic graph processing method. Background technique [0002] With the advent of the big data era, graph processing systems have gradually become important. As a data structure, a graph has a strong expressive ability in terms of structure and semantics, and can well describe the relationship between things. By abstracting relational properties in the real world into graph data structures, graph processing systems are able to execute graph algorithms to analyze these graph data. For example, the importance ranking of graph vertices can be carried out through the PageRank algorithm; the accessibility relationship between graph vertices can be obtained through the strongly connected component algorithm. [0003] However, since the relationship between things in the real world changes every moment, which makes the graph dat...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/50G06F15/78G06F16/901
CPCG06F9/5027G06F15/7867G06F16/9024G06F2209/5018G06F30/343G06F2117/08G06F2209/509Y02D10/00G06F9/4881G06F9/505G06F9/5066G06F2209/5017
Inventor 廖小飞陈意诚张宇金海赵进赵祥司贝贝
Owner HUAZHONG UNIV OF SCI & TECH
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