High density substrate and stacked silicon package assembly having same

Abstract

Embodiments of the invention relate to a high density substrate and a stacked silicon package assembly having the same. An improved interconnect substrate having high density routings for a chip package assembly, a chip package assembly having a high density substrate, and methods for fabricating the same are provided that utilize substrates having a region of high density routings disposed over aregion of low density routings. In one example, a method for fabricating an interconnect substrate is provided that includes forming a high density routing region by depositing a seed layer on a topsurface of a low density routing region, patterning a mask layer on the seed layer, forming a plurality of conductive posts on the seed layer, removing the mask layer and the seed layer exposed between the conductive posts, and depositing a dielectric layer between the between the conductive posts, wherein at least some of the conductive posts are electrically coupled to conductive routing comprising the low density routing region.

Description

technical field [0001] Examples of the present disclosure generally relate to a substrate for a chip package, and more particularly, to a substrate having high-density wiring for a chip package, and a chip package having the substrate. Background technique [0002] Electronic devices, such as tablets, computers, copiers, digital cameras, smart phones, control systems, and automated teller machines, etc., often employ electronic components that utilize chip-package components for increased functionality and higher component density. Conventional chip packaging solutions typically utilize a packaging substrate (often in combination with a through-silicon via (TSV) interposer) to enable multiple integrated circuit (IC) die to be mounted to a single packaging substrate. An IC die may include memory, logic, or other IC devices. [0003] In many chip packaging assemblies, high density wiring on organic packaging substrates or interposers (collectively referred to as substrates) i...

AI Technical Summary

Problems solved by technology

In such applications, the memory and logic die may operate at temperatures very close to the thermal junction temperature limit, exacerbating stress levels and leading to device failure

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