MOS device with annular channel region and preparation method thereof

Abstract

The invention discloses an MOS device with an annular channel region and a preparation method of the MOS device, belongs to the technical field of MOS devices, and solves the problems of short channeleffect, gate control capability and saturation current reduction of a planar MOS device with a small size (such as nanoscale) in the prior art. The MOS device comprises a source electrode, a drain electrode, a grid electrode and a channel region, the drain electrode is located on the periphery of the source electrode, the channel region is located between the source electrode and the drain electrode, and the channel region is annular; and a plurality of channels are formed in the surface of the channel region in the direction from the source to the drain, and the grid is located in the channels. The preparation method comprises the following steps: forming a source electrode and a drain electrode; forming a channel region between the source electrode and the drain electrode; etching the surface of the channel region along the direction from the source electrode to the drain electrode, and extending a channel material to form a channel; and forming a gate in the channel. According to the MOS device and the preparation method thereof, the area of a current channel can be expanded, and the saturation current is improved.

Description

technical field [0001] The present application relates to a MOS device, in particular to a MOS device with an annular channel region and a preparation method thereof. Background technique [0002] With the continuous miniaturization of semiconductor devices, in order to meet the design requirements for turn-on voltage and saturation current, three-dimensional devices (such as Finfet and nanowires, etc.) are becoming the development direction of the industry. However, because the 3D device process (for example, Fin manufacturing process) is relatively complex and requires high equipment capabilities, in comparison, the planar device process still has considerable cost and process advantages, and will coexist with 3D devices for a considerable period of time. . [0003] In the existing planar device technology, a symmetrical source-drain structure is generally adopted. However, as the channel size continues to decrease, especially after entering the nanometer scale, the short...

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Problems solved by technology

[0004] In view of the above-mentioned analysis, the present application aims to provide a MOS device with an annular channel region and its preparation method, which solves the short-channel effect of the planar MOS device with a smaller size (for example, nanoscale) and the gate gap in the prior art. The problem of control ability and saturation current drop

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