Compensation method and device for bit line leakage current of static random access memory

Abstract

The invention provides a compensation method for bit line leakage current of a static random access memory. The compensation method comprises the following steps: collecting discharge current of two adjacent bit lines; and controlling the voltage of the bit line with relatively large discharge current in the two adjacent bit lines to be reduced, and / or controlling the voltage of the bit line withrelatively small discharge current in the two adjacent bit lines to be increased. According to the compensation method for the bit line leakage current of the static random access memory, less time isneeded when the SA can detect the voltage, the read working time is shortened, and the working speed of the circuit is increased. In the same read clock window, the SA can detect a larger voltage difference.

Description

technical field [0001] The invention relates to the technical field of compensation for bit line leakage current of SRAM, in particular to a compensation method and device for bit line leakage current of SRAM. Background technique [0002] As a typical storage structure, Static Random Access Memory (SRAM) has been widely used in Logic Large Scale Integration (LSI). This is because SRAM has the advantages of fast operation speed and low static power consumption, and at the same time, SRAM can use the same manufacturing process as logic circuits. As an important part of logic LSI, SRAM will directly affect the performance and yield of the entire circuit. As the scale of the circuit becomes larger and the process node becomes more advanced, it will bring side effects to the circuit. One of the biggest problems is that as the process node decreases, the leakage of the bit line increases, and the increase of leakage will affect the operation of the SRAM. , especially the discha...

AI Technical Summary

Problems solved by technology

However, increasing the compensation transistor in the SRAM unit will increase the area of ​​the SRAM unit, and the use of capacitance compensation will increase the load capacitance of the bit line. At the same time, the current sampling sequence is required, which affects the readout rate.

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