Instruction scheduling method and system for multi-cycle instruction and medium

Abstract

The invention discloses an instruction scheduling method and system for a multi-period instruction and a medium. The method comprises the steps that the multi-period instruction and a dependent instruction thereof are recognized after instruction decoding; reading a priority scheduling instruction buffer, if a corresponding record exists in the priority scheduling instruction buffer, judging thata data dependence relationship exists between the current instruction and a certain multi-cycle instruction, and marking the current instruction as a priority scheduling instruction; when the instruction is renamed, writing address information of the instruction on which the multi-cycle instruction depends into a priority scheduling buffer; and preferentially transmitting an instruction marked asa preferentially transmitted instruction when the instruction is transmitted. According to the method, the instruction parallelism characteristic in the high-performance out-of-order microprocessor isfully explored, the multi-cycle instruction is executed as early as possible through instruction scheduling for the multi-cycle instruction, the performance of the processor is improved, the implementation cost is low, and the method can be conveniently integrated into an existing processor design.

Description

technical field [0001] The invention relates to the field of processor microarchitecture design, in particular to an instruction scheduling method, system and medium for multi-cycle instructions. Background technique [0002] In the design of high-performance microprocessors, in order to improve the performance of the program, it is usually necessary to fully explore the parallelism of the program instruction level. When there is no correlation between multiple instructions, they can be executed in parallel in the pipeline, and the execution time of the entire program can be shortened by parallel execution in different components, thereby improving program performance. When there is data dependence in the program, that is, when the input of an instruction depends on the output of another instruction, the two instructions cannot be parallelized, and the data consumption instruction can only be executed after the execution of the data generation instruction is completed. When...

AI Technical Summary

Problems solved by technology

Although multiple components are set in the processor to allow ALU and MXU components to execute instructions in parallel, instruction I5 cannot be executed in parallel with other instructions because the source operand of instruction I5 is not ready.

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