A silicon connection layer test circuit for testing by using a test die

Abstract

The application provides a silicon connection layer test circuit for testing by using a test die, which relates to the field of semiconductor technology. JTAG control logic and boundary scan test chains are arranged inside the test die to form a test circuit, and the test die and the silicon connection layer The connection points of the same arrangement are arranged on the surface, so that when the test die is placed on the carrier and the surface of the silicon connection layer is attached, the connection between the connection points can be realized, so that the test circuit inside the test die can be used to complete the silicon connection. The test stimulus transmission and test result capture of the signal path structure in the layer can easily realize the test of the silicon connection layer and quickly screen the silicon connection layer before assembly to ensure that the silicon connection layer with normal functions can be assembled with the bare chip in the later stage. Normal multi-die silicon stack interconnect structure to ensure production yield.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a silicon connection layer test circuit for testing by using a test bare chip. Background technique [0002] FPGA (Field Programmable Gate Array, Field Programmable Logic Gate Array) is a hardware programmable logic device. In addition to being used in mobile communications, data centers and other fields, it is also widely used in prototype verification in integrated circuit design, which can effectively verify The correctness of the circuit function, while speeding up the circuit design speed. Prototype verification requires the use of programmable logic resources inside the FPGA to implement circuit design. With the continuous increase in the scale of integrated circuits and the realization of complex functions, the demand for the number of programmable logic resources in FPGAs continues to increase. Subsequent technology development and demand As the number of FPGA pro...

AI Technical Summary

Problems solved by technology

Prototype verification requires the use of programmable logic resources inside the FPGA to implement circuit design. With the continuous increase in the scale of integrated circuits and the realization of complex functions, the demand for the number of programmable logic resources in FPGAs continues to increase. Subsequent technology development and demand As the number of FPGA programmable resources continues to increase, it will become a greater bottleneck, posing greater challenges to the development of the industry

The increase in FPGA scale means that the chip area continues to increase, which will lead to an increase in the difficulty of chip processing and a decrease in chip production yield.

[0003] At present, some patents have proposed the method of chip interconnection design through silicon stacked interconnection technology (SSI). Later, it was discovered that the function of the silicon connection layer was abnormal and the entire FPGA was affected, and the production yield was difficult to guarantee.

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