A general-purpose structured silicon connection layer with built-in test circuits

Abstract

The application discloses a silicon connection layer with a general structure of a built-in test circuit, which relates to the field of semiconductor technology. Several silicon connection layer input connection points and silicon connection layer output connection points are arranged on the surface of the silicon connection layer. The JTAG control logic and the boundary scan test chain are arranged to form a test circuit. The boundary scan test chain includes several boundary scan cell structures connected to the JTAG control logic in series in sequence, and each boundary scan cell structure is connected to a corresponding connection point; JTAG The control logic can complete the test stimulus transmission and test result capture through the boundary scan test chain, and can realize the test of the silicon connection layer to quickly screen the silicon connection layer before assembly, so as to ensure that the normal function of the silicon connection layer and the bare metal can be used later. Chips are assembled to form a normal multi-die silicon stack interconnection structure to ensure production yield.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a silicon connection layer with a general structure of built-in test circuits. Background technique [0002] FPGA (Field Programmable Gate Array, Field Programmable Logic Gate Array) is a hardware programmable logic device. It is not only used in mobile communication, data center and other fields, but also widely used in prototype verification in integrated circuit design, which can effectively verify The correctness of circuit function, while speeding up circuit design. Prototype verification needs to use the programmable logic resources inside FPGA to realize circuit design. With the continuous increase of the scale of integrated circuits and the realization of complex functions, the demand for the number of programmable logic resources of FPGA is constantly increasing. With the continuous increase, the number of FPGA programmable resources will become a greater bottlen...

AI Technical Summary

Problems solved by technology

Prototype verification requires the use of programmable logic resources inside the FPGA to implement circuit design. With the continuous increase in the scale of integrated circuits and the realization of complex functions, the demand for the number of programmable logic resources in FPGAs continues to increase. Subsequent technology development and demand As the number of FPGA programmable resources continues to increase, it will become a greater bottleneck, posing greater challenges to the development of the industry

The increase in FPGA scale means that the chip area continues to increase, which will lead to an increase in the difficulty of chip processing and a decrease in chip production yield.

[0003] At present, some patents have proposed a method of chip interconnection design through silicon stacked interconnection technology (SSI). Later, it was discovered that the function of the silicon connection layer was abnormal and the entire FPGA was affected, and the production yield was difficult to guarantee.

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