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Interlayer dielectric layer structure for power MOS device and manufacturing method of interlayer dielectric layer structure

A technology of MOS devices and interlayer dielectric layers, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve the problem of large power MOS device leakage, and achieve the effect of reducing source-drain leakage current

Inactive Publication Date: 2020-09-29
HUA HONG SEMICON WUXI LTD
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Problems solved by technology

[0004] The present application provides an interlayer dielectric layer structure for power MOS and its manufacturing method, which can solve the problem that in the related art, movable ions can pass through the silicon dioxide interlayer dielectric film and enter the channel position, which will cause the power MOS The problem of excessive device leakage

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  • Interlayer dielectric layer structure for power MOS device and manufacturing method of interlayer dielectric layer structure
  • Interlayer dielectric layer structure for power MOS device and manufacturing method of interlayer dielectric layer structure
  • Interlayer dielectric layer structure for power MOS device and manufacturing method of interlayer dielectric layer structure

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[0023] The technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

[0024] In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, use a specific orientati...

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Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to an interlayer dielectric layer structure for a power MOS device and a manufacturing method of the interlayer dielectric layer structure. The interlayer dielectric layer structure for the power MOS device comprises a silicon-rich oxide SiOx thin film layer deposited on the surface of the power MOS device,and a silicon dioxide thin film layer is deposited on the silicon-rich oxide SiOx thin film. The manufacturing method of the interlayer dielectric layer structure for the power MOS device is characterized by comprising the following steps: depositing the silicon-rich oxide SiOx thin film layer on the surface of the power MOS device; and depositing a silicon dioxide film layer on the silicon-rich oxide SiOx thin film layer. The invention can solve the problem that movable ions can penetrate through a silicon dioxide interlayer dielectric film to enter a channel position, so that electric leakage of the power MOS device is large.

Description

technical field [0001] This application relates to the technical field of semiconductor manufacturing, and specifically relates to an interlayer dielectric layer structure for power MOS devices and a manufacturing method thereof. Background technique [0002] With the development of integrated circuit technology, the size of integrated circuits is also continuously reduced according to Moore's law, which requires continuous improvement of technology to support the ever-increasing product requirements. With the improvement of IC technology, the 12-inch production line began Capable of producing power MOS devices. [0003] For related technologies, a silicon dioxide interlayer dielectric film is usually formed between the power MOS device and the first metal layer to isolate and insulate the device. However, for medium and high voltage power MOS devices, a large number of mobile ions will be generated in the back-end process of the interlayer dielectric film, and these mobile...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/532H01L21/768
CPCH01L23/53295H01L21/76829H01L21/76832
Inventor 刘秀勇陈正嵘吴长明张继亮金立培
Owner HUA HONG SEMICON WUXI LTD
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