Thinned wafer packaging process using TSV and TGV

Abstract

The invention discloses a thinning wafer packaging process utilizing TSV and TGV. The process comprises the following steps: S1, enabling a wafer to be bonded with a glass carrier plate, and forming aTSV communication hole in the back surface; S2, electroplating the TSV communication hole to form a Ni / Pd / Cu seed layer; S3, filling the TSV communication hole with Cu; S4, manufacturing a wafer copper column bump; S5, electroplating a Ni / Pd / Au metal laminated layer; S6, manufacturing a TGV communication hole in the back surface of the glass carrier plate; S7, electroplating the TGV communicationhole to form a Ni / Pd / Cu seed layer; S8, filling the TGV communication hole with Cu to form a copper column bump; S9, forming an RDL on the back surface of the glass carrier plate; S10, performing etching to remove the redundant Ni / Pd / Cu seed layer; S11, electroplating a Ni / Pd / Au metal laminated layer on the surface of the copper column bump of the glass carrier plate; and S12, welding connectinglines of the TSV and the TGV to Clip or Board respectively, and completing the 3D architecture. According to the method, TSV / TGV flat hole filling electroplating of a Cu CMP procedure is not needed,TSV and TGV communication hole connecting wires are manufactured on the front face and the back face respectively to be in double-face wiring connection, Clip or Board can be welded up and down, and a3D framework with high integration degree and low delay conduction is completed.

Description

technical field [0001] The invention relates to the field of wafer processing, in particular to a thinning wafer packaging process utilizing TSV and TGV. Background technique [0002] With the rise of communication electronics, people's demand for miniaturized and high-sensitivity modules or systems is getting higher and higher, and the requirements for signal quality are becoming more and more stringent. High-density integration technologies, such as System-in-Package (SiP) technologies, have developed rapidly, but miniaturized integrated packaging of mixed-signal multi-chip systems has become one of the technical difficulties in this field. The new 3D packaging technology represented by system-in-package, in addition to technologies such as three-dimensional chip stacking (Stacked Diepackage), package stacking (Package on Package, POP), the application of some new materials and new technologies brings opportunities for packaging miniaturization, For example, flexible subs...

AI Technical Summary

Problems solved by technology

[0005] Traditional ECP technology fills and connects TSVs or TGVs. After filling metal into the through-silicon vias (TSVs), CMP chemical mechanical polishing technology can be used to remove the metal layer on the outer surface of the via holes to achieve the planarization of via filling. In the structure of ultra-thin wafers or glass substrates, the use of CMP will limit the thickness of the substrate. If it is too thin, it will cause uneven stress and cause fragmentation or mechanical damage.

Images