LDMOS device and manufacturing method thereof

Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to an LDMOS device and a manufacturing method thereof. The method comprises the following steps: providing asemiconductor substrate, and forming a shallow trench isolation structure around the semiconductor substrate of the device, wherein the shallow trench isolation structure extends downwards from the front face of the semiconductor substrate; forming a drift region in the semiconductor substrate surrounded by the shallow trench isolation structure; forming a body region in the drift region of the source end region of the device; forming a gate structure bridged between the body region and the drain terminal region; forming a high-voltage LDD region in the drift region of the drain terminal region of the device; forming side walls at the side edges of the gate structures of the connector region and the high-voltage LDD region respectively; respectively forming a source region and a drain region in the body region and the high-voltage LDD region, wherein the source region and the drain region form overlapping regions with the corresponding side walls, wherein the device is manufactured bythe method.

Description

technical field [0001] The present application relates to the technical field of semiconductor manufacturing, in particular to an LDMOS device and a manufacturing method thereof. Background technique [0002] DMOS (Double-diffused MOS) is currently widely used in power management circuits due to its characteristics of high voltage resistance, high current drive capability and extremely low power consumption. Lateral double-diffused metal oxide semiconductor field effect transistor (LateralDouble-diffused MOS, LDMOS) is a kind of DMOS, and one of the main inspection parameters is on-resistance (Rds-on). On-resistance refers to when the device is working, Resistance from drain to source. For LDMOS devices, reducing the on-resistance as much as possible is the goal pursued by the BCD process. Due to the small on-resistance between the drain and source, the LDMOS device will have better switching characteristics and a larger output current, which can have a stronger drive capa...

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Problems solved by technology

[0004] Although the LDMOS device of the related art includes a high-voltage-resistant drift region 113 and a high-voltage well region that can improve the device drain current concentration effect, as the size of the polysilicon gate of the device becomes smaller and smaller, the non-autonomous high-voltage well region Alignment implantation will lead to large deviation of characteristic parameters between devices on the wafer, which is not conducive to reliability optimization

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