High-voltage three-dimensional depletion super-junction LDMOS device and manufacturing method thereof

Abstract

The invention provides a high-voltage three-dimensional depletion super-junction LDMOS and a manufacturing method thereof. The high-voltage three-dimensional depletion super-junction LDMOS comprises asecond conductive type substrate, a first conductive type drift region, a first conductive type well region, a second conductive type well region, a first dielectric oxide layer, a second conductivetype buried layer, a second dielectric oxide layer, and a first conductive type region and a second conductive type region which form a super junction, wherein the second conductive type buried layerand the super junction structure are both located in the first conductive type drift region, and the super junction is located above the second conductive type buried layer and connected with the second conductive type buried layer; the second conductive type buried layer optimizes the surface electric field of the device in an off state; the second conductive type buried layer and the super-junction second conductive type region surround the super-junction first conductive type region from three sides to form a three-dimensional depletion super-junction structure Fin-SJ structure, the dopingconcentration of the first conductive type drift region and the super-junction first conductive type region is allowed to be improved, the super-junction structure provides a surface low-resistance path, and the specific on-resistance of the device is reduced.

Description

technical field [0001] The invention belongs to the technical field of semiconductor process manufacturing, and in particular relates to a novel high-voltage three-dimensional depletion superjunction LDMOS device (Fin-SJ LDMOS device) and a manufacturing method thereof. Background technique [0002] Because of its high input impedance, low loss, fast switching speed, wide safe operating area and easy integration, high-voltage LDMOS has always been used as a core device in power integrated circuits, and is widely used in mobile communications, automotive electronics, LED lighting, etc. in the field. The performance of high-voltage LDMOS often requires that it can withstand high voltage while reducing the specific on-resistance as much as possible. In order to achieve this goal, the existing commonly used technologies include lateral superjunction and surface field reduction (RESURF) technology, all of which are passed in the drift region. The opposite charge compensation lay...

AI Technical Summary

Problems solved by technology

However, the drift region of the conventional superjunction and RESURF technology only comes from the auxiliary depletion of the charge compensation layer on both sides, and its improvement of device performance is getting closer and closer to the limit. How to further increase the compensation ability of the charge compensation layer and improve the doping of the drift region The impurity concentration, to further reduce the specific on-resistance while ensuring the withstand voltage, is the core issue of device improvement.

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