Manufacturing method of high-dielectric-constant metal gate

Abstract

The invention discloses a method for manufacturing a high-dielectric-constant metal gate, which comprises the following steps of: 1, providing a semiconductor substrate, and forming a pseudo gate structure and a first interlayer film; 2, photoetching to open a PMOS formation region; 3, performing back etching to reduce the height of the top surface of the PMOS formation region so as to counteractthe influence of one more P-type work function layer in the gate trench in the PMOS formation region on the depth-to-width ratio of the gate trench in subsequent metal gate filling; 4, removing the pseudo polysilicon gate and forming a gate trench; 5, filling each gate trench with a metal gate, the metal gate of the PMOS comprising a P-type work function layer, an N-type work function layer and agate conductive material layer which are stacked in sequence, and the metal gate of the NMOS comprising an N-type work function layer and a gate conductive material layer which are stacked in sequence; and 6, carrying out a second planarization process to enable the top surfaces of the NMOS and PMOS forming regions on which the metal gates are formed to be flush with each other. According to the invention, the filling process window and the filling quality of the metal gate of the PMOS can be improved.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing a high dielectric constant metal gate (HKMG). Background technique [0002] With the development of CMOS technology, traditional silicon dioxide gate dielectric and polysilicon gate (Poly SiON) transistors have reached physical limits, such as the problem of excessive leakage current due to quantum tunneling effect and the depletion of polysilicon gate problems, etc. seriously affect the performance of semiconductor devices. Starting from the 45nm technology node, the HKMG stacked transistor developed on the basis of the HKMG process effectively solves the above technical problems. [0003] The applicant has adopted the mainstream metal gate-last (Gate-Last) deposition and front-gate dielectric (HK-First) deposition processes in the industry at the 28nm high dielectric constant metal gate technology node. In this process...

AI Technical Summary

Problems solved by technology

Since PMOS, that is, PFET, has an extra layer of P-type work function layer TiN film, the aspect ratio becomes very large during subsequent filling, which can easily lead to sidewall and top overhang effects, resulting in the failure of subsequent Al filling, resulting in Al hole

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