Common-mode level switching high-speed comparator

Abstract

The embodiment of the invention provides a common-mode level switching high-speed comparator, which adopts a two-stage latch structure, a first-stage pre-amplifier is driven by a high clock signal CLKH, a first-stage latch circuit and a second-stage latch circuit are driven by a low clock signal CLKL, the first-stage pre-amplifier adopts a high power supply voltage. The first-stage latch circuit and the second-stage latch circuit adopt low power supply voltage, the common-mode input level of the comparator is improved by raising the power supply voltage and the clock of the first-stage pre-amplifier, and the output common-mode range is reduced to the low-level range by the latch circuits of the later two stages, so that the problems of distortion and breakdown are avoided while the speed of the comparator is increased, the overall performance of the digital-to-analog converter ADC can be improved.

Description

technical field [0001] The invention relates to the field of circuit electronics, in particular to a common-mode level switching high-speed comparator. Background technique [0002] With the advancement of chip technology, the power supply voltage of the circuit is decreasing, and the design of the operational amplifier in the analog-to-digital converter (ADC) becomes difficult. In order to reduce the design difficulty, the method of increasing the power supply voltage can be used to improve the performance of the operational amplifier. Use this This method generally results in a relatively high common-mode output level of the op amp, so a comparator with a high common-mode input level needs to be connected to it. The comparator is composed of a first-stage pre-amplifier and a latch circuit. Since the typical breakdown voltage and stress tolerance of the MOS do not exceed 130% of the power supply voltage, the first-stage pre-amplifier and the latch circuit use the same power...

AI Technical Summary

Problems solved by technology

[0002] With the advancement of chip technology, the power supply voltage of the circuit is decreasing, and the design of the operational amplifier in the analog-to-digital converter (ADC) becomes difficult. In order to reduce the design difficulty, The method of increasing the power supply voltage can be used to improve the performance of the op amp. Using this method will generally cause the common mode output level of the op amp to be relatively high, so it is necessary to use a comparator with a high common mode input level to connect with it.

The comparator is composed of a first-stage pre-amplifier and a latch circuit. Since the typical breakdown voltage and stress tolerance of the MOS do not exceed 130% of the power supply voltage, the first-stage pre-amplifier and the latch circuit use the same power supply. When the power supply voltage is When the voltage is low, the comparator cannot be connected to a high common-mode input level. When the power supply voltage is high, the reliability of the internal devices of the comparator is reduced, and the power consumption of the comparator is high, and the performance of the analog-to-digital converter is accordingly Reduced, so a comparator with higher reliability and performance

Images