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Semiconductor structure and forming method thereof

A semiconductor and patterning technology, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of different etching load effects, pattern bridging, pattern transfer distortion, etc., to reduce the etching load effect, Uniform appearance and accurate size

Pending Publication Date: 2021-04-30
CHANGXIN MEMORY TECH INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In the process of multi-pattern support, the sidewall is usually formed by deposition and etching processes, and an arc-shaped shape will be formed at the corner of the sidewall on the top side of the sidewall, which makes the shape of the sidewall on both sides of the sidewall different. In the pattern transfer process, the pattern 104a and pattern 104b on both sides of the sidewall layer have different effects on the etching ions due to their different shapes and sizes, which will produce different etching load effects, which will cause pattern transfer distortion and cause critical dimension Problems with misalignment or even pattern bridging

Method used

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  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof

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Embodiment Construction

[0026] Specific implementations of the semiconductor structure and its forming method provided by the present invention will be described in detail below in conjunction with the accompanying drawings.

[0027] Please refer to figure 2 , providing a substrate 200, and forming a patterned sacrificial layer 210 on the surface of the substrate 200.

[0028] In this specific embodiment, the base 200 includes a substrate 201 and a target layer 202 on the surface of the substrate 201 .

[0029] The material of the substrate 201 is semiconductor materials such as silicon, germanium, silicon germanium, silicon carbide or indium gallium; the substrate 201 can also be a silicon-on-insulator substrate, a germanium-on-insulator substrate or an on-insulator substrate. silicon germanium substrate. In this specific embodiment, the substrate 201 is a single crystal silicon substrate.

[0030] Semiconductor devices such as MOS transistors, resistors, capacitors or inductors may also be form...

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Abstract

The invention relates to a semiconductor structure and a forming method thereof. The forming method comprises the following steps: providing a substrate; forming a graphical sacrificial layer on the surface of the substrate; forming a first side wall on the surface of the side wall of the sacrificial layer; removing the sacrificial layer; filling second side walls between the adjacent first side walls, wherein the tops of the second side walls are lower than the tops of the first side walls; etching the first side walls to the surface of the substrate to form a plurality of discrete second side walls; and etching the substrate by taking the second side wall as a mask. According to the forming method, the accuracy of the etched pattern formed after the substrate is etched can be improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] With the continuous reduction of the size of semiconductor devices, in order to improve the integration of devices, a double patterning process is proposed. The double patterning technology only needs to make small changes to the existing lithography infrastructure, which can effectively fill the gap of lithography technology for smaller nodes, improve the minimum pitch between adjacent semiconductor patterns, and thus obtain Smaller feature size, higher density graphics. The principle of dual patterning technology is to decompose a set of high-density patterns into two separate sets of lower-density patterns, and then prepare them on the wafer. The double patterning technologies in the prior art mainly include: self-aligned double patterning (SADP: Self-Aligned Double-Patterning), seco...

Claims

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Application Information

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IPC IPC(8): H01L21/033H01L21/027H01L21/28H01L29/423
CPCH01L21/0274H01L21/0332H01L21/28247H01L29/42356
Inventor 董鹏
Owner CHANGXIN MEMORY TECH INC
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