Chip design optimization system and method based on dynamic unbalanced clock

Abstract

The invention provides a chip design optimization system and method based on a dynamic unbalanced clock. In a designed synthesis stage, a designed time sequence path is analyzed, clock delay of a time sequence unit is analyzed and dynamically adjusted according to a current time sequence result, and a clock delay result is transmitted to subsequent steps of a chip design implementation process, so that an unbalanced clock tree structure is synthesized according to requirements during clock tree synthesis. The delay of the whole leaf node clock network is dynamically adjusted in the synthesis and layout wiring stage in the chip design implementation process, so that the purpose of quickly converging the time sequence is achieved. Due to the fact that the dynamic unbalanced clock network is used, the time sequence path of chip design has more time sequence allowance, a chip implementation tool can better optimize the whole designed time sequence, the path with tense time sequence does not need more complex optimization, and therefore the area of the whole design is reduced, power consumption is reduced, and cost is reduced. The achievable clock speed of the design is improved, and the design performance is improved.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a chip design optimization system and method based on a dynamic unbalanced clock. Background technique [0002] The integrated circuit design and implementation process includes a synthesis stage and a layout and routing stage. In the synthesis stage, in the traditional process, the clock is ideal, and the delay from the clock source to different registers is the same, only from the timing constraints of the design. Use the clock uncertainty (Clock Uncertainty) to be constrained. This kind of constraint is relatively arbitrary, and it is difficult to meet the design constraint requirements for some timing paths with relatively tight timing requirements. However, in the implementation process, if such a timing path has a timing margin in the forward timing path or the backward timing path, the timing path can be made Meet the final design requirements. T...

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Problems solved by technology

[0003] Aiming at the shortage of balanced clock tree in the existing chip design and implementation process, the present invention proposes a chip design optimiz

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