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Low quiescent current off-chip capacitor-free LDO with dynamically optimized power supply rejection ratio

A power supply rejection ratio and no off-chip capacitor technology, applied in the direction of high-efficiency power electronic conversion, regulation of electrical variables, control/regulation systems, etc., can solve the problems of high power consumption, large area, complex structure, etc., to achieve reduced area, The effect of reducing the area and improving the transient response performance

Active Publication Date: 2021-06-11
ZHEJIANG UNIV
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  • Abstract
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Problems solved by technology

[0004] Aiming at the problems of large area, high power consumption and complex structure in the above PSR optimization scheme, the present invention proposes a PSR adaptive optimization scheme suitable for CL-LDO

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  • Low quiescent current off-chip capacitor-free LDO with dynamically optimized power supply rejection ratio
  • Low quiescent current off-chip capacitor-free LDO with dynamically optimized power supply rejection ratio
  • Low quiescent current off-chip capacitor-free LDO with dynamically optimized power supply rejection ratio

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Embodiment Construction

[0042] The present invention will be further described below in conjunction with accompanying drawing:

[0043] The analysis and optimization of PSR are carried out first. There are multiple paths between the power supply and the LDO output, allowing power supply noise to couple into the output, limiting PSR. figure 1 In the schematic diagram of , there are three main noise coupling paths: (1) error amplifier (EA, ErrorAmplifier); (2) power transistor gate-source parasitic capacitance (C gs ); (3) The drain body parasitic capacitance of the power tube (C db ) and drain-source conductance (g ds ). The power supply noise of the first two paths is first coupled to the M pass gate, then M pass Transconductance (g m ) is amplified and converted into a noise current.

[0044] exist figure 2 In the small-signal model of , the parasitic capacitance is split into two ground-dividing capacitances and two voltage-controlled current sources. To optimize PSR, power supply noise c...

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Abstract

The invention discloses a low quiescent current off-chip capacitor-free LDO with a dynamic optimization power supply rejection ratio. An LDO circuit comprises an LDO main module and a PSR optimization module; the LDO main module is used for providing a stable output voltage when a load current or an input voltage changes; and the PSR optimization module injects a frequency-related compensation current into a grid electrode of a power tube in the LDO main module and is used for optimizing the intermediate-frequency PSR of the LDO. According to the low-quiescent-current off-chip capacitor-free LDO with the dynamic optimization power supply rejection ratio, a power tube copy tube is not needed, and the advantage of low quiescent current is achieved; and the feed-forward compensation current is dynamically adjusted by monitoring the working state of the power tube, so that the flexibility is higher.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, in particular to a low quiescent current LDO with no off-chip capacitance and a dynamically optimized power supply rejection ratio. Background technique [0002] As a key component of power management, a voltage regulator provides an adjustable, stable and low-noise voltage, and is widely used in a system on chip (SoC, System on Chip). A linear low-dropout regulator (LDO, Low-Dropout Regulator) is a type of voltage regulator, which has better resistance to power supply noise than a switched capacitor or a switching regulator. According to the position of the main pole, LDO is divided into two types: external compensation and internal compensation. The former main pole is located at the LDO output, and the latter is located inside the LDO. Internally compensated LDO, also known as CL-LDO (Capacitor-less LDO), has the advantages of small area and high integration because...

Claims

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Application Information

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IPC IPC(8): G05F1/56
CPCG05F1/56Y02B70/10
Inventor 张培勇徐叶
Owner ZHEJIANG UNIV
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