Manufacturing method of semiconductor device
A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device testing/measurement, electrical components, etc., can solve the problems of low yield rate of semiconductor chips, affecting the final yield rate and reliability of semiconductor chips, etc. , to achieve the effect of improving the yield of finished products
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Embodiment 1
[0076] In the embodiment of the present application, the preset time is located after the etching stopper layer 31 is fabricated and before the first dielectric layer 32 is formed. In the embodiment of the present application, as Figure 4 As shown, if the detection result of the semiconductor device does not meet the first condition, removing the dielectric layer 3 includes:
[0077] Step 211: Reference Figure 5 , if the detection result of the semiconductor device does not meet the first condition, and the thickness of the etching barrier layer is less than a first preset value, forming a buffer layer 4 on the surface of the etching barrier layer 31;
[0078] Step 212: Reference Image 6 , polishing the buffer layer 4 and the etch stop layer 31 until the etch stop layer 31 is removed.
[0079] Specifically, in an embodiment of the present application, the first preset value is 200 angstroms, but the present application does not make a limitation on this, and it depends on...
Embodiment 2
[0104] In the embodiment of the present application, the preset time is after the first dielectric layer 32 is formed. Optionally, in the embodiment of the present application, the thickness of the etching barrier layer is less than the first preset value, However, this application does not limit it, and it depends on the specific circumstances.
[0105] Specifically, in one embodiment of this application, as Figure 8 As shown, if the detection result of the semiconductor device does not meet the first condition, removing the dielectric layer 3 includes:
[0106] Step 221: Reference Figure 9 , etching a portion of the first dielectric layer 32 to retain the first dielectric layer 321 of the first thickness;
[0107] Step 222: Reference Figure 10 , polishing the first dielectric layer 321 of the first thickness and the etch stop layer 31 until the etch stop layer 31 is removed.
[0108] It should be noted that, in the embodiment of the present application, the etch stop ...
Embodiment 3
[0127] In the embodiment of this application, refer to Figure 11 , the dielectric layer 3 further includes a photoresist pattern 5 located on the side of the first dielectric layer 32 facing away from the etching barrier layer 31; the preset time is located after the formation of the photoresist pattern 5, refer to Figure 12 , in the embodiment of the present application, if the detection result of the semiconductor device does not meet the first condition, removing the dielectric layer 3 includes:
[0128] Step 231: Reference Figure 13 , removing the photoresist pattern 5;
[0129] Step 232: Reference Figure 14 , etching a portion of the first dielectric layer 32 to retain the first dielectric layer 321 of the first thickness;
[0130] Step 233: Reference Figure 15 , polishing the first dielectric layer 321 of the first thickness and the etch stop layer 31 until the etch stop layer 31 is removed;
[0131] Wherein, the first thickness is smaller than the thickness o...
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Abstract
Description
Claims
Application Information
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