A phase-locked loop circuit and its control method, semiconductor device and electronic equipment

Abstract

The embodiment of the present invention discloses a phase-locked loop circuit, including: a phase frequency comparison unit, which compares the phase of the external reference clock signal with the phase of the comparison clock signal, and generates an error signal corresponding to the comparison result; an oscillation unit, which generates the oscillation frequency An internal clock signal corresponding to the error signal; a frequency division unit, which divides the frequency of the internal clock signal with a preset frequency division ratio to generate the comparison clock signal; a control unit, which divides the phase of the external reference clock signal After comparing with the phase of the comparison clock signal, a control signal for respectively changing the circuit connection between the oscillation unit and the frequency division unit is generated. The phase-locked loop circuit provided by the embodiment of the present invention can automatically detect the locking of the phase-locked loop circuit and correct the wrong locking and harmonic locking of the phase-locking loop circuit. When it is wrongly locked, it does not need to be reset again to ensure that the phase of its output does not change abruptly, nor does it generate additional spike signals, which will affect the integrity of the clock signal.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a phase-locked loop circuit and its control method, a semiconductor device and electronic equipment including the phase-locked loop circuit. Background technique [0002] Between the stand-alone machines of the data communication system, it is often necessary to transmit the clock, and perform frequency multiplication or frequency division processing on the clock. Since the jitter index of the transmission clock is not ideal, the traditional method is to use a hardware phase-locked loop (PLL: Phase Locked Loop) circuit to implement clock loop tracking, or use a delay phase-locked loop circuit (DLL: delay locked loop). A delay-locked loop circuit is a circuit that can output a periodic signal that has the same period as the input clock signal and has a certain time delay. [0003] The core component of the delay-locked loop is the voltage-controlled delay line (VCDL: volta...

AI Technical Summary

Problems solved by technology

When there is only waveform alignment, the frequency of the output signal and the input signal are not in multiples, and the digital algorithm finds that the output frequency of the delay chain is too different from the demand value, then configure the delay unit delay of the delay chain to the minimum, and let the delay chain lock again. But this will cause abnormal duty cycle or glitch in the delay chain, when the output of the delay-locked loop circuit is used for the system clock, it may cause errors in the system digital algorithm

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